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參數(shù)資料
| 型號(hào)： | QS5917T-132TJ |
| 廠商： | QUALITY SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | GIGATRUE 550 CAT PATCH CBL SNAGLSS 1FT BG 25 PK |
| 中文描述： | PLL BASED CLOCK DRIVER, PQCC28 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | QS5917T-132TJ |
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3
Pin Names
SYNC
0
SYNC
1
REF_SEL
FREQ_SEL
FEEDBACK
I/O
I
I
I
I
I
Description
Reference clock input
Reference clock input
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs.
Asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled (normal
operation).
PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).
No Connection
Q
0
-Q
4
Q
5
2xQ
Q/2
LOCK
RST
O
O
O
O
O
I
PLL_EN
NC
I
—
PIN DESCRIPTION
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/
V
DD
= 5V ± 5%
Symbol
F
2XQ
F
Q
F
Q/2
Description
Max Frequency, 2xQ output
Max Frequency, Q
0
- Q
4
, Q
5
outputs
Max Frequency, Q/2
output
– 70
70
35
17.5
– 100
100
50
25
– 132
132
66
33
Units
MHz
MHz
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QS5917T-132TQ | GIGATRUE 550 CAT6 PATCH 2 FT, SNAGLESS, BEIGE |
| QS5917T | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TJ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TQ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919-55TQX | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5917T-132TJ8 | 制造商:Integrated Device Technology Inc 功能描述:Clock Generators & Support Products CLK DRVR PLL, FILTER |
| QS5917T-132TJG | 制造商:Integrated Device Technology Inc 功能描述:IDT QS5917T-132TJG PLL - Rail/Tube |
| QS5917T-132TJG8 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28PLCC - Tape and Reel |
| QS5917T-132TQ | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Rail/Tube |
| QS5917T-132TQ8 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Tape and Reel |
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