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參數(shù)資料
| 型號： | QS5917T-132TQ |
| 廠商： | QUALITY SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | GIGATRUE 550 CAT6 PATCH 2 FT, SNAGLESS, BEIGE |
| 中文描述： | PLL BASED CLOCK DRIVER, PDSO28 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 62K |
| 代理商： | QS5917T-132TQ |
INDUSTRIAL TEMPERATURE RANGE
4
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
SYNC (MHz)
(allowable range)
Min.
14
28
28
56
7
14
14
Output Used for
Feedback
Q/2
Q
0
-Q
4
Q
5
2xQ
Q/2
Q
0
-Q
4
Q
5
Output Frequency Relationships
Q
5
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
– SYNC X 2
– SYNC
SYNC
FREQ_SEL
1
1
1
1
0
0
0
Max
F
2XQ
/
4
F
2XQ
/
2
F
2XQ
/
2
F
2XQ (1)
F
2XQ
/
8
F
2XQ
/
4
F
2XQ
/
4
Q/
2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
Q Outputs
SYNC X 2
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
– SYNC
2XQ
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
0
2xQ
28
F
2XQ
/
2
SYNC / 4
– SYNC / 2
SYNC / 2
SYNC
NOTE:
1. For the –132 speed grade, maximuminput frequency is restricted to 100MHz.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage Level
Guaranteed Logic HIGH level
2
—
—
V
V
IL
V
OH
Input LOW Voltage Level
Output HIGH Voltage
Guaranteed Logic LOW level
V
DD
= Min., I
OH
=
24mA
(1)
V
DD
= Min., I
OH
=
100
μ
A
V
DD
= Min., I
OL
= 24mA
(1)
V
DD
= Min., I
OL
= 100
μ
A
V
OUT
= V
DD
or GND, V
DD
= Max.
V
IN
= AV
DD
or GND, AV
DD
= Max.
—
2.4
3
—
—
—
—
—
—
—
—
—
—
—
0.9
—
—
0.55
0.2
±5
±5
V
V
V
OL
Output LOW Voltage
V
I
OZ
I
IN
Output Leakage Current
Input Leakage Current
μ
A
μ
A
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, A
VDD
/V
DD
= 5V ± 5%
NOTE
:
1. I
OL
and I
OH
are 12mA and –12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
Max.
Unit
I
CC
Input Power Supply Current per TTL Input HIGH
(2)
V
DD
= Max., V
IN
= 3.4V
V
DD
= Max
0.4
1.5
mA
I
CCD
Dynamc Power Supply Current
—
0.4
mA/MHz
NOTES:
1. For conditions shown as Mn. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QS5917T | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TJ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5917T-70TQ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919-55TQX | Eight Distributed-Output Clock Driver |
| QS5919-70TJ | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5917T-132TQ8 | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Tape and Reel |
| QS5917T-132TQG | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CLK DRVR PLL, FILTER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| QS5917T-132TQG8 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin QSOP T/R 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER. QSOP28 - Tape and Reel |
| QS5917T-132TQX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5917T-70TJ | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin PLCC Tube 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28PLCC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:CLK DRVR PLL, FILTER - Bulk |
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