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參數(shù)資料
| 型號： | QS5919T70J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 129K |
| 代理商： | QS5919T70J |
5
INDUSTRIAL TEMPERATURE RANGE
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
(1)
Mn.
—
2.5
2
25
Max.
3
Unit
ns
MHz
ns
%
Maximuminput rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
Input clock pulse, HIGH or LOW
(2)
Input duty cycle
(2)
F
MAX _2XQ
—
75
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
SKALL
t
PW
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
(1)
Mn.
—
—
—
Max.
350
350
500
Unit
ps
ps
ps
ns
ns
ns
ps
ms
ns
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/
2
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/
2
(2)
Output Skew, All Outputs
(2,5)
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q
0
-Q
4
, Q
5,
Q/
2
outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(6)
SYNC to Phase Lock
Output Enable Time, OE/
RST
LOW to HIGH
(3)
T
CY
/2
0.4
T
CY
/2
0.4
0.15
500
—
0
T
CY
/2 + 0.4
T
CY
/2 + 0.4
0.15
0
10
7
Output Enable Time, OE/
RST
HIGH to LOW
(3)
0
6
ns
Output Rise/Fall Times, 0.8V
～
2V
0.3
1.5
ns
NOTES:
1. See Test Loads and Waveforms for test load and termination. Test circuit 1 is used for output enable/disable parameters. Test circuit 2 is used for all
other timing parameters.
2. Skew specifications apply under identical environments (loading, temperature, V
CC
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input
frequencies.
5. Skew measured at selected synchronization edge.
6. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
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相關代理商/技術參數(shù) |
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|---|---|
| QS5919T-70J | 制造商:Integrated Device Technology Inc 功能描述:QS5919T-70J - Bulk |
| QS5919T70Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919T-70TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5919T-70TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5920AQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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