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參數(shù)資料
| 型號(hào)： | QS5930-50TQ |
| 廠商： | QUALITY SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | PLL BASED CLOCK DRIVER, PDSO20 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大小： | 57K |
| 代理商： | QS5930-50TQ |
2
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AV
DD
V
DD
AGND
SYNC
FREQ_SEL
GND
Q
0
Q
4
Q/2
GND
Q
3
Q
2
GND
PLL_EN
GND
Q
1
V
DD
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
AV
DD
,V
DD
Supply Voltage to Ground
DC Input Voltage V
IN
AC Input Voltage (for pulse width
≤
20ns)
MaximumPower Dissipation (T
A
= 85°C)
T
STG
Storage Temperature Range
Rating
Max.
–0.5 to +7
–0.5 to +7
–3
1
–65 to +150
Unit
V
V
V
W
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACIT ANCE
(T
A
= 25
°
C, f = 1MHz, V
IN
= 0V)
Pins
Typ.
3
7
Max.
4
9
Unit
pF
pF
C
IN
C
OUT
PIN DESCRIPTION
Pin Name
SYNC
FREQ_SEL
I/O
I
I
Description
Reference clock input
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher
frequencies, LOW is for lower frequencies.
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in phase, but frequency is half the Q frequency.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for systemdebug.
Power supply for output buffers.
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
Ground supply for phase lock loop and other internal circuitries.
FEEDBACK
I
Q
0
-Q
4
Q/2
OE/
RST
O
O
I
PLL_EN
V
DD
AV
DD
GND
AGND
I
—
—
—
—
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/V
DD
= 5V ± 10%
Symbol
F
MAX_Q
F
MAX_Q/2
F
MIN_Q
F
MIN_Q/2
Description
Max Frequency, Q
0
- Q
4
,
Max Frequency, Q/2
Mn Frequency, Q
0
- Q
4
Mn Frequency, Q/2
– 50
50
25
28
14
– 66
66
33
28
14
Units
MHz
MHz
MHz
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5930-66TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| QS5930T | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5931-50Q | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Six Distributed-Output Clock Driver |
| QS5931-66Q | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Six Distributed-Output Clock Driver |
| QS5931-80Q | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Six Distributed-Output Clock Driver |
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