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參數(shù)資料
| 型號： | QS5930T |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 低偏移的CMOS PLL時鐘驅動器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 57K |
| 代理商： | QS5930T |
5
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
300
7.0V
OUTPUT
V
DD
OUTPUT
160
68
28pF
AC TEST LOADS AND WAV EFORMS
TEST CIRCUIT 1
TEST CIRCUIT 2
SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK
Q/2
Q
VCO/2
/2
PHASE
DETECTOR
INPUT
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T
provides for replication of incomng SYNC clock signals. Any manipu-
lation of that signal, such as frequency multiplying, is performed by
digital logic following the PLL (see the block diagram). The key advan-
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back,
it will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5930T typically provides within 150ps of
phase shift between input and output.
tage of the PLL circuit is to provide an effective zero propagation delay
between the output and input signals. In fact, adding delay circuits in
the feedback path, ‘propagation delay’ can even be negative! A simpli-
fied schematic of the QS5930T PLL circuit is shown below:
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for
feedback will be advanced by the amount of delay in the feedback
path. All other outputs will retain their proper relationships to that output.
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