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參數(shù)資料
| 型號： | QS5931-66Q |
| 英文描述： | Six Distributed-Output Clock Driver |
| 中文描述： | 六分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 92K |
| 代理商： | QS5931-66Q |
2
INDUSTRIAL TEMPERATURE RANGE
QS5935
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AV
DD
AGND
CLK_IN
V
DD
GND
Q
0
Q
4
N/C
GND
Q
3
Q
2
GND
PLL_EN
GND
Q
1
V
DD
V
DD
SO20-8
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
AV
DD,
V
DD
Rating
Max.
–0.5 to +7
–0.5 to V
DD
+0.5
0.5
–65 to +150
Unit
V
V
W
°C
Supply Voltage to Ground
DC Input Voltage V
IN
MaximumPower Dissipation (T
A
= 85°C)
Storage Temperature Range
T
STG
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
°
C, f = 1MHz, V
IN
= 0V)
(1)
Pins
Typ.
3
4
Max.
4
5
Unit
pF
pF
C
IN
C
OUT
NOTE:
1. Capacitance is characterized but not tested.
PIN DESCRIPTION
Pin Name
CLK_IN
FEEDBACK
Q
0
-Q
4
OE/
RST
I/O
I
I
O
I
Description
Reference clock input
External feedback provides flexibility for different output frequency relationships
Clock outputs
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
When 1, PLL is enabled. When 0, PLL is disabled and the output for Q
0
-Q
4
will be CLK_IN/2 in frequency. This allows the
CLK_IN input to be single-stepped for systemdebug.
Power supply for output buffers
Power supply for phase lock loop and other internal circuitries
Ground supply for output buffers
Ground supply for phase lock loop and other internal circuitries
PLL_EN
I
V
DD
AV
DD
GND
AGND
—
—
—
—
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| QS5931-80Q | Six Distributed-Output Clock Driver |
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| QS5991-2JR | Eight Distributed-Output Clock Driver |
| QS5991-2TJ | Eight Distributed-Output Clock Driver |
| QS5991-2TJX | Eight Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| QS5931-80Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Six Distributed-Output Clock Driver |
| QS5931Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SIX DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|20PIN|PLASTIC |
| QS5935Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Four Distributed-Output Clock Driver |
| QS59910-2SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS59910-2SOX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
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