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參數(shù)資料
| 型號(hào)： | QS5LV919 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 3.3V的低偏移的CMOS PLL時(shí)鐘驅(qū)動(dòng)器，帶有集成環(huán)路濾波器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | QS5LV919 |
4
INDUSTRIAL TEMPERATURE RANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTES:
1.
Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_2
X
Q
. Operation with Sync inputs outside
specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
The 2xQ is limted to a maximumfrequency (F
MAX_2XQ
) of 100MHz only when used as a feedback.
2.
3.
FREQUENCY SELECTION TABLE
SYNC (MHz)
(allowable range)
(1)
Min.
F
MIN_Q/2
F
MIN_Q
F
MIN_Q
F
MIN_2XQ
F
MIN_Q/2
/2
F
MIN_Q
/2
F
MIN_Q
/2
F
MIN_2XQ
/2
Output Used for
Feedback
Q/2
Q
0
-Q
4
Q
5
2xQ
(3)
Q/2
Q
0
-Q
4
Q
5
2xQ
Output Frequency Relationships
(2)
Q
5
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
FREQ_SEL
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Max
Q/
2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
Q
0
- Q
4
SYNC X 2
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
2XQ
F
MAX _Q/2
F
MAX _Q
F
MAX _Q
100
F
MAX _Q/2
/2
F
MAX _Q
/2
F
MAX _Q
/2
F
MAX _2XQ
/2
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
Symbol
V
IH
V
IL
V
OH
Parameter
Conditions
Min.
2
—
V
DD
– 0.6
V
DD
– 0.2
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
100
—
—
—
Max.
—
0.8
—
—
0.45
0.2
—
± 5
± 5
± 100
Unit
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
I
OH
=
24mA
I
OH
=
100
μ
A
V
DD
= Mn., I
OL
= 24mA
V
DD
= Mn., I
OL
= 100
μ
A
—
V
OUT
= V
DD
or GND, V
DD
= Max.
AV
DD
= Max., V
IN
= AV
DD
or GND
AV
DD
= Max., V
IN
= AV
DD
V
OL
Output LOW Voltage
V
V
H
I
OZ
I
IN
I
PD
Input Hysteresis
Output Leakage Current
Input Leakage Current
Input Pull-Down Current (
PE
)
mV
μ
A
μ
A
μ
A
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
I
DDQ
Quiescent Power Supply Current
Test Conditions
V
DD
= Max., OE/
RST
= LOW,
SYNC = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3V
V
DD
= Max., C
L
= 0pF
Typ.
Max.
1
Unit
mA
I
DD
I
DDD
Power Supply Current per Input HIGH
Dynamc Power Supply Current
(1)
1
30
0.4
μ
A
0.2
mA/MHz
NOTE:
1. Relative to the frequency of Q outputs.
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Industrial: T
A
= -40°C to +85°C, AV
DD
/V
DD
= 3.3V ± 0.3V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5LV919100J | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919100Q | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919-100Q | 制造商:Integrated Device Technology Inc 功能描述: 制造商:QSI 功能描述: |
| QS5LV919133J | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV919133Q | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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