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參數(shù)資料
| 型號： | QS5LV93180Q |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 3.3V的低偏移的CMOS PLL時鐘驅(qū)動器，帶有集成環(huán)路濾波器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | QS5LV93180Q |
2
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
AV
DD
/V
DD
Supply Voltage to Ground
DC Input Voltage V
IN
MaximumPower Dissipation (T
A
= 85°C)
T
STG
Storage Temperature Range
Max
Unit
V
V
W
°C
–0.5 to +7
–0.5 to +5.5
0.5
–65 to +150
QSOP
TOP VIEW
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Pins
Typ.
C
IN
3
C
OUT
4
Max.
4
5
Unit
pF
pF
PIN DESCRIPTION
Pin Name
SYNC
FREQ_SEL
I/O
I
I
Description
Reference clock input
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies,
LOW is for lower frequencies.
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in phase, but frequency is half the Q frequency.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are
enabled.
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for systemdebug.
Power supply for output buffers
Power supply for phase lock loop and other internal circuitries
Ground supply for output buffers
Ground supply for phase lock loop and other internal circuitries
FEEDBACK
I
Q
0
-Q
4
Q/2
OE/
RST
O
O
I
PLL_EN
V
DD
AV
DD
GND
AGND
I
—
—
—
—
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/V
DD
= 3.3V ± 0.3V
Symbol
F
MAX_Q
F
MAX_Q/2
F
MIN_Q
F
MIN_Q/2
Description
Max Frequency, Q
0
- Q
4
,
Max Frequency, Q/2
Mn Frequency, Q
0
- Q
4
Mn Frequency, Q/2
– 50
50
25
10
5
– 66
66
33
10
5
– 80
80
40
10
5
Units
MHz
MHz
MHz
MHz
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AV
DD
V
DD
AGND
SYNC
FREQ_SEL
GND
Q
1
Q
4
Q/2
GND
Q
3
Q
2
GND
PLL_EN
GND
Q
1
V
DD
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QS5LV931-80Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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| QS5U12_1 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2.5V Drive Nch+SBD MOS FET |
| QS5U12TR | 功能描述:MOSFET N-CH 30V 2A TSMT5 RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| QS5U13 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Small switching (30V, 2.0A) |
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