參數(shù)資料
型號(hào)： QT60160-ATG
廠(chǎng)商： Atmel
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 0K
描述： IC TOUCH SENSOR 16KEY 32QFN
標(biāo)準(zhǔn)包裝： 3,000
系列： QMatrix™
類(lèi)型： 電容性
輸入數(shù)/鍵： 16 鍵
分辨率（位）： 10 b
評(píng)估套件： 可供
數(shù)據(jù)接口： I²C，串行，SPI?
電壓基準(zhǔn)： 外部
電源電壓： 1.8V，3.3V，5V
電流 - 電源： 4.6mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN
供應(yīng)商設(shè)備封裝： 32-QFN
包裝： 帶卷 (TR)
其它名稱(chēng)： QT60160-ATG-ND
QT60160-ATGTR
Table 4.2 Bits for Key Reporting and Numbering
16
17
18
19
20
21
22
23
3
8
9
10
11
12
13
14
15
2
0
1
2
3
4
5
6
7
1
0
1
2
3
4
5
6
7
Bit Number
Address
Note: the device should be reset after disabling keys
because, if a key was in detect when it was disabled, it could
incorrectly report detect.
4.5 Raw Data Commands
Addresses 4 to 123 allow data to be read for each key. There
are a total of 24 keys and 5 bytes of data per key, yielding a
total of 120 addresses. These addresses are read-only.
The data for the keys is mapped in sequence, starting with
key 0 at addresses 4 to 8. The data for key 15 is located at
addresses 79 to 83, and that for key 23 is located at
addresses 119 to 123. Table 4.3 summarizes this.
There are five bytes of data for each key. The first two are the
key’s 16-bit signal, and the second two are the key’s 16-bit
reference. These are followed by the Detect Integrator Count,
which is a 4-bit value stored in the lower nibble. In the case of
both the signal and reference, the 16-bit values are accessed
as two 8-bit bytes, stored LSB first.
4.6 Cal All
A value of 0x55 must be written to address 125. Upon
receiving this command the QT60xx0 will recalibrate all of the
keys. Recalibration will start at the beginning of the next full
matrix scan and last for one scan cycle.
4.7 Setups
The location “Setups write-unlock”, address 130, allows write
access to the setups. Normally the setups are write-protected;
the write-protection is engaged as soon as a read operation is
performed at any address. By writing a value of 0x55 to this
address, the write-protection is disengaged. This address is
located conveniently immediately before the setups so that
the write protection may be disengaged and the setups
written in a single I2C communication sequence. Reading this
address is undefined.
Addresses 131 to 252 provide read/write access to the
setups. Details of different setups can be found in Section 6,
page 17.
When the host is writing a new setup block the values are
being recorded into EEPROM as they arrive from the host.
lQ
13
QT60240-ISG R8.06/0906
DetectCount (lower nibble)
23
123
Reference MSB
23
122
Reference LSB
23
121
Signal MSB
23
120
Signal LSB
23
119
Range of values
3 to 22
19 to 118
DetectCount (lower nibble)
2
18
Reference MSB
2
17
Reference LSB
2
16
Signal MSB
2
15
Signal LSB
2
14
DetectCount (lower nibble)
1
13
Reference MSB
1
12
Reference LSB
1
11
Signal MSB
1
10
Signal LSB
1
9
DetectCount (lower nibble)
0
8
Reference MSB
0
7
Reference LSB
0
6
Signal MSB
0
5
Signal LSB
0
4
Use
Key #
Address
Table 4.3 Key Data
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