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參數(shù)資料
| 型號： | R3118N411A-TR-FE |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5 |
| 封裝： | HALOGEN AND LEAD FREE, SOT-23, 5 PIN |
| 文件頁數(shù)： | 21/23頁 |
| 文件大小： | 481K |
| 代理商： | R3118N411A-TR-FE |
R3118x
7
DEFINITION OF OUTPUT DELAY TIME
A higher voltage than the released voltage is forced to the SENSE pin, charge to the capacitor connected to
CD pin is started, then the CD pin voltage increases. Until CD pin voltage reaches to CD pin threshold voltage, the
output of DOUT pin voltage keeps "L", then when CD pin voltage is higher than CD pin threshold voltage, the DOUT
pin voltage changes from "L" to "H". The released output delay time means the time interval from when the
released voltage threshold or more voltage level is forced to SENSE pin to when DOUT voltage changes from "L"
to "H".
When the voltage of DOUT pin reverses from "L" to "H", the discharge of the external capacitor connected to
CD pin starts. Therefore, the time interval from when the voltage lower than the detector threshold is forced to
SENSE pin, to when the output voltage reverses from "H" to "L", or detector output delay time is constant and
independent from the external capacitance value.
1. After the DOUT pin voltage reverses from "L" to "H", if a voltage lower than the detector threshold is forced to
SENSE pin before the capacitor connected to CD pin is discharged, delay time will increase. The time
interval (tDIS) from when the capacitor connected to CD pin is discharged completely to when the capacitor is
charged to a certain CD pin voltage (described as VCD herein) can be calculated by power supply voltage
(VDD), external capacitance (CD), on resistance of the CD pin discharge transistor (RDIS) as in the next
formula:
tDIS
=-RDIS×CD×ln(VCD/VDD×0.45))
2. During the released delay operation, only a small current will charge the external capacitor connected to CD
pin. If the leakage current between CD pin and GND is large, the released delay time may increase or the
detector may not be released.
3. During the released delay operation, if the VDD pin voltage varies, the released output delay time will be also
shift.
How to calculate the released output delay time
The release output delay time (tdelay) can be calculated as in the next formula with an external capacitance
value (CD):
tdelay(s)
=4.545×106×CD(F)
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