參數(shù)資料
型號: R5F5630EDDFB#V0
廠商: Renesas Electronics America
文件頁數(shù): 89/165頁
文件大?。?/td> 0K
描述: MCU RX630 2MB FLASH 144-LQFP
產(chǎn)品培訓模塊: RX Compare Match Timer
RX DMAC
標準包裝: 1
系列: RX600
核心處理器: RX
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,LIN,SCI,SPI,USB
外圍設備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 117
程序存儲器容量: 2MB(2M x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b,21x12b,D/A 2x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
R01DS0060EJ0100 Rev.1.00
Page 3 of 168
Sep 13, 2011
RX630 Group
1. Overview
Interrupt
Interrupt control unit
(ICUb)
Peripheral function interrupts: 180 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16- or 32-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller
(DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
I/O ports
Programmable I/O ports
177-pin TFLGA (in planning), 176-pin LFBGA (in planning), 176-pin LQFP
I/O pins: 148
Input pin: 1
Pull-up resistors: 148
Open-drain outputs: 148
5-V tolerance: 54
145-pin TFLGA (in planning), 144-pin LQFP
I/O pins: 117
Input pin: 1
Pull-up resistors: 117
Open-drain outputs: 117
5-V tolerance: 53
100-pin TFLGA (in planning), 100-pin LQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 44
80-pin LQFP
I/O pins: 58
Input pin: 1
Pull-up resistors: 58
Open-drain outputs: 58
5-V tolerance: 34
Table 1.1
Outline of Specifications (2/5)
Classification
Module/Function
Description
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