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型號(hào)：	R80C52EXXX-16D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)：	321/849頁(yè)
文件大?。?/td>	12530K
代理商：	R80C52EXXX-16D

32099I–01/2012

AT32UC3L016/32/64

Slave Node Configuration

In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier

from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the

write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.

IMPORTANT: if in slave mode, NACT is already configured correctly as PUBLISH, the LINMR

sponding Peripheral DMA Controller write transfer.

Figure 19-35. Slave Node with Peripheral DMA Controller

Wake-up Request

Any node in a sleeping LIN cluster may request a wake-up. By writing to the Wakeup Signal

Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.3 (WKUPTYP=1), or a

LIN 2.0 (WKUPTYP=0) compliant wakeup request. Writing a one to the Send LIN Wakeup Sig-

nal bit (CR.LINWKUP), transmits a wakeup, and when completed sets LINTC.

According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order

to impose eight successive dominant bits.

According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for

250s to 5ms. Sending the character 0xF0 does this, regardless of baud rate.

Baud rate max = 20 kbit/s -> one bit period = 50s -> five bit periods = 250s

Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms

Bus Idle Time-out

LIN bus inactivity should eventually cause slaves to time-out and enter sleep mode. LIN 1.3

specifies this to 25000 bit periods, whilst LIN 2.0 specifies 4seconds. For the time-out counter

NACT = SUBSCRIBE

WRITE BUFFER

Peripheral DMA

Peripheral DMA

Table 19-9.

Receiver Time-out Values (RTOR.TO)

LIN Specification

Baud Rate

Time-out period

19 200 bit/s

20 000 bit/s

25 000 bit periods

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