47
7530J–AVR–03/12
Atmel ATmega48/88/168 Automotive
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Note:
1. Values are guidelines only. Actual values are TBD.
8.2
Watchdog Timer
ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The main features are:
Clocked from separate On-chip Oscillator
3 Operating modes
–Interrupt
– System Reset
– Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 8-7.
Watchdog Timer
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator.
The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset
- instruction to restart the counter before the time-out value is reached. If the system doesn't
restart the counter, an interrupt or system reset will be issued.
Table 8-4.
Internal Voltage Reference Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
VBG
Bandgap reference voltage
TBD
1.0
1.1
1.2
V
tBG
Bandgap reference start-up time
TBD
40
70
s
IBG
Bandgap reference current consumption
TBD
10
TBD
A
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT