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參數(shù)資料
| 型號： | RC5033M |
| 廠商： | Raytheon Company |
| 元件分類： | DC/DC變換器 |
| 英文描述： | Adjustanble Sychronous DC-DC Converter |
| 中文描述： | Adjustanble Sychronous的DC - DC轉換器 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 186K |
| 代理商： | RC5033M |
RC5033
PRODUCT SPECIFICATION
13
P
9V by using the bootstrap capacitor C2. When the lower FET
M2 is turned on, one side of the capacitor C2 is connected to
GND while the other side of the cap is being charged up
through D2 to a voltage that is Vin - Vd. When the lower
FET turns off and the upper one turns on, the voltage that is
supplied to the VCCQP pin is 2Vin - Vd. The voltage then
that is applied to the gate of the FET is VCCQP - Vsat, typi-
cally around 9V. It is important in the selection of DS1 and
DS2 that they have a low forward voltage drop as this
directly affects the regulator efficiency. The other job that
DS2 performs is that of bootstrapping VCCQP during star-
tup. It is possible to cause the output stage to latchup if the
VCCQP supply is brought up before the other VCC supplies
of the RC5033. It is therefore advisable that DS2 be con-
nected even in applications that do not utilize the bootstrap-
ping technique for VCCQP. An alternate application could
tie the VCCQP supply pin to the +12V power supply in the
PC, thus eliminating the need for C2 and forcing the Rdson
of M1 even lower by increasing its Vgs.
MOSFET Switches
The MOSFET switches in the RC5033 applications circuit
are N-channel “l(fā)ogic-level” FETs. This means that they will
be fully on with a Vgs of 4V. Many manufacturers make
logic-level FETs and the trick is to choose the one with the
lowest
RDSon at
the given Imax current level. The value of
RDSon directly enters into the efficiency equation as a power
loss. Also influencing the efficiency is the gate charge of the
FET and the clock frequency of the RC5033. At higher
clocking rates the amount of charge needed to be delivered to
the FET is going to lower the overall efficiency. In higher
current applications, the upper FET can be paralleled to pro-
vide greater current capability; however, the lower FET
doesn’t necessarily have to be doubled since it is on only a
fraction of the time that the upper FET is on.
PCB Layout and Grounding
As is the case with most analog circuitry, good layout
practices are necessary to achieve the optimum in the overall
performance of the DC-to-DC converter. In general, it is
always a good practice to have a tight layout that attempts to
minimize short low inductance wiring to the RC5033.
The use of multilayer PCB is recommended. In particular, it
is recommended to have a continuos ground plane beneath
the circuit, 2oz copper would be preferred in high current
applications. As was stated previously, the current-sense
resistor, R1, should be located as close to the RC5033 as
possible and the IFB and VFB traces should be Kelvin con-
nected to the pads of R1. To minimize switching losses and
noise, place M1, M2, L and DS2 as close together as possi-
ble. Also try to keep the HIDRV and LODRV gate drive sig-
nal traces as short as possible. It is recommended that the
noisy switching part of the circuit be kept away from the low
current pins on the chip such as IFB, VFB, ADJ3, ADJ1, and
CEXT. Keep the 0.1uF bypass capacitors as close to the chip
pins as possible. All of the ground pins should be connected
to the ground plane directly under the chip. A sample layout
is provided in Figure 6.
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