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參數(shù)資料
| 型號： | REJ03F0059_M61533FP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | LEAD FREE EXT TEMP A6841 SOIC-20 |
| 中文描述： | 4通道電子音量帶AGC |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 374K |
| 代理商： | REJ03F0059_M61533FP |
M61533FP
Rev.1.0, Sep.19.2003, page 6 of 12
Timing Definition of Digital Block
Parameter
CLOCK cycle time
CLOCK pulse width(“H” level)
CLOCK pulse width (“L” level)
Rising time of clock and data
Falling time of clock and data
DATA setup time (Rising time of clock)
DATA setup time (Falling time of clock)
DATA hold time(“H” level)
DATA hold time(“L” level)
Data Control Specification
Symbol
tcr
tWHC
tWLC
tr
tf
tSHD
tSLD
tHHD
tHLD
Limits
Min.
4
1.6
1.6
0.8
0.8
0.8
0.8
Typ.
Max.
0.4
0.4
Unit
μ
s
Four types of input format can be selected by changing the D14/D15 slot setting status.
(Initialize all data of the 4 formats when power supply(VCC) turn on.)
(1)
(2)
D0a D1a
2
D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 D15
SWch
Output gain
control
(3)
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10bD11bD12bD13b D14 D15
SLch Master volume
SLch Trim volume
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15
SRch Master volume
0
0
0
0
1
0
0
0
0
0
1
1
Cch Trim volume
(4)
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10dD11dD12dD13d D14 D15
SWch Master volume
Cch Master volume
SRch Trim volume
0
0
0
0
0
1
0
0
SWch Trim volume
1
0
0
0
0
1
Note : No guarantee except for these code.
2
2
2
1
3
3
3
3
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