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參數(shù)資料
| 型號(hào)： | RESILIENTRINGPROCESSOR |
| 英文描述： | Rhea -OC-48/OC-192 SRP MAC for Resilient Packet Rings |
| 中文描述： | 瑞亞-OC-48/OC-192 SRP的陸委會(huì)的彈性分組環(huán) |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 647K |
| 代理商： | RESILIENTRINGPROCESSOR |
■
Automatic pass-through/wrap/
transparent mode communication
■
Requires only 1 standard SERDES for
inter-board communication
■
Loss of sync detection with
performance counters
■
CRC detection
P
R O D U C T
B
R I E F
N e v e r s t o p t h i n k i n g .
MATE Interface
■
XGMII 10 gigabit interface
■
4, 8-bit channels at 312.5 MHz
(10.0 Gbit/s total capacity)
Microprocessor Interface
■
16-bit, asynchronous interface, up to
100 MHz
■
Multiple interrupt reporting
■
Send and receive buffers for IPS and
topology packets
Electrical/Mechanical/Thermal
■
1.5/1.8/3.3 V power supplies
■
899-pin Hyper BGA Flip Chip
package
■
-40 °C to 85
°
C operation
■
~5.18 W
Other
■
JTAG Compliant
■
100 MHz or 200 MHz reference clock
■
Hard and soft reset
■
CRC generation and checking
■
Extensive loopback features for
testing
Key Features
■
High speed SRP MAC
■
Up to OC-192 (10 Gbit/s) throughput
■
Supports SRP, POS, Native Ethernet
■
1 MB low-priority transit buffer
■
32 KB high-priority transit buffer
■
Giant, runt and short packet filters
■
Supports IPS and topology discovery
■
899-pin Hyper BGA package
Specifications
Modes of Operation
■
Dual ring mode
■
Wrap mode
■
Pass-through mode
■
Transparent mode
■
Passive and active sniffer modes
Operational Speeds
■
OC-192
■
OC-48
Packet Formats
■
SRP
■
Pseudo-SRP
■
POS (in transparent mode)
■
Native Ethernet
RX/TX Framer
Host Interface
■
64-bits HSTL @200 MHz
■
OIF SPI-4 Phase 1 compliant interface
■
Giant, runt and short packet filtering
with PM counters
■
Data and control parity bit checking
with PM counters
■
Traffic flow monitoring
■
Host-side leaky bucket rate limiters -
high/low priority
■
Data parity fault insertion for system
and software test
■
Counters for high/low priority
unicast/multicast packets and bytes
Lookup / Statistics
CAM Functions
■
1024 Double (source, destination or
both) address entries
■
1024 Double address counters
■
CAM S/W features: read/write/
probe/reset individual entries
■
8 coarse multicast address filters
accept or reject on match
■
Multicast accept/reject capability
for individual addresses
Transit Buffer
■
Internal source and sink for usage
packets
■
Internal 1 MB low and 32 KB high
priority buffers
■
Counters for high/low priority
unicast/multicast packets and bytes
■
Counters for min, max and average
delay in transit buffers
R h e a
R e s i l i e n t R i n g P r o c e s s o r
O C - 4 8 / O C - 1 9 2 S R P M A C
Semiconductor Solutions for
High Speed Communications
and Fiber Optic Applications
The Infineon Resilient Ring Processor is a packet opti-
mized transport engine designed to enable the first
generation of Resilient Packet Rings (RPR) for metro-
politan area networks. Its feature-rich design supports
spatial reuse protocol (SRP) at speeds up to 10 Gbit/s.
It incorporates packet support for both POS and native
Ethernet with the flexibility to transport across SONET,
DWDM or dark fiber. The Infineon Resilient Ring Proces-
sor is uniquely positioned to enable cost-effective resil-
iency and QoS for growing, high-speed IP networks.
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