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參數(shù)資料
| 型號： | RF105 |
| 英文描述： | 900 MHz Digital Spread Spectrum Transceiver |
| 中文描述： | 900兆赫數(shù)字?jǐn)U頻收發(fā)器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 119K |
| 代理商： | RF105 |
RF105
900 MHz Digital Spread Spectrum Transceiver
4
Conexant
W117, Rev. B
September 28, 1999
Conexant Proprietary Information
Synthesizer Programming ________________________
The synthesizer is programmed with a half-duplex 3-wire
serial interface. The three signals are DATA, CLK, and
STROBE. Each rising edge of the CLK signal shifts one bit
of the data into the shift register and control register. When
the STROBE input is toggled from low to high, the data
latched in the shift register is transferred to the
programmable counter. Six bits are shifted into the
synthesizer for programming. The data format is as
follows:
MSB
S6
LSB
S1
S5
S4
S3
S2
The timing relationship is shown in Figure 6. The values of
the programming bits, S1 to S6, for the programmable
counter are defined in Table 1.
Channel Selection
Using a 9.6 MHz reference frequency, the Phase Locked
Loop (PLL) synthesizer can generate frequencies from
903 MHz (Channel 1) to 927 MHz (Channel 41) at a
channel spacing of 600 kHz. The LO frequency (F
LO
) is
calculated by the following equation:
F
LO
= (F
REF
/R) × [(M × N) + A]
where:
F
REF
is 9.6 MHz (reference oscillator)
R is 16 (reference divider)
M is 32/33 (prescaler)
N is 47 (fixed counter)
A is 1 to 41 (programmable counter)
Examples:
(9.6 MHz / 16) × (32 × 47 + 1) = 903 MHz
(9.6 MHz / 16) × (32 × 47 + 41)= 927 MHz
Synthesizer Loop Filter
The VCO for the synthesizer is designed on-chip with the
varactor referenced to VCC. Therefore,
the loop filter
components will need to be tied to VCC4
(pin 39) instead
of ground. A typical loop filter design is shown below in
Figure 5. The loop bandwidth is approximately 5 kHz with a
nominal phase margin of 45 degrees.
0.01μF
10k
VCO
TUNE
330
pF
390
pF
10k
CHPO
pin 43
Figure 5. Loop Filter
t1
t2
t3
t5
t4
MSB
LSB
DATA
CLK
STROBE
t1 =Data setup time
t2 =Data hold time
t3 =Clock pulse-width
t4 =STROBE enable pulse-width
t5 =STROBE setup time to the rising edge of the last clock
t1 to t5 1μs each.
Figure 6. Timing Diagram
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