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參數(shù)資料
| 型號： | RF2679 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 204K |
| 代理商： | RF2679 |
Preliminary
7-42
RF2679
Rev A0 000825
7
Q
D
Pin
12
Function
FCLK
Description
Reference clock for base band filters.
Interface Schematic
13
Q OUT-
Balanced Baseband Output of Q Mixer. This pin is internally DC biased
and should be DC blocked externally. The output can be used in a sin-
gle-ended configuration by leaving one of the two pins unconnected,
however half the output voltage will be lost.
14
15
16
17
Q OUT+
GND2
I OUT-
I OUT+
Same as pin 13, except complementary output.
See pin 13.
Ground connection for the baseband stage.
Same as pin 17, except complementary output.
See pin 17.
Balanced Baseband Output of I Mixer. This pin is internally DC biased
and should be DC blocked externally. The output can be used in a sin-
gle-ended configuration by leaving one of the two pins unconnected,
however half the output voltage will be lost.
18
19
20
IDCFB
QDCFB
CALEN
DC feedback capacitor for in-phase channel.
DC feedback capacitor for quadrature channel.
Calibration enable for BB filters. Calibration is performed when CALEN
goes high. The calibration takes approximately 100
μ
s, consumes
0.5mA, and is totally independent of the ENABLE pin. Once calibration
is complete, the calibration word is stored and the calibration circuit is
disabled. If the CALEN pin goes low of V
CC
is disabled, then the cali-
bration word is lost and the IC needs recalibration.
Balanced AGC Output/Demod Input. This balanced node is pinned out
to allow shunt filtering of the AGC output signal as it enters the demod-
ulator. The basic configuration of the filter should consist of a shunt
inductor and shunt capacitor, both connected to the power supply, as
the internal circuitry requires this power supply connection through the
inductor to operate.
21
FL-
22
23
FL+
Same as pin 21, except complementary.
See pin 21.
ENABLE
Power Down Control. When logic “high” (
≥
V
CC
-0.3V), all circuits are
operating; when logic “l(fā)ow” (
≤
0.5V), all circuits are turned off.
Bandgap Voltage Reference. This voltage, constant over temperature
and supply variation, is used to bias internal circuits. A 10nF external
bypass capacitor is required. The trace length between the pin and the
bypass capacitor should be minimized. The ground side of the bypass
capacitor should connect immediately to ground plane.
24
BG OUT
300
150
μ
A
Q OUT-
Q OUT+
V
CC
V
CC
150
μ
A
150
μ
A
I OUT-
I OUT+
150
μ
A
V
CC
V
CC
1.2 k
1.2 k
V
CC2
V
CC2
FL+
FL-
V
CC1
V
CC1
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