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參數(shù)資料
| 型號： | RF2705PCBA-41X |
| 廠商： | RF Micro Devices, Inc. |
| 英文描述： | 887664400 |
| 中文描述： | 低噪聲，多模，四頻，正交調(diào)制器及PA驅(qū)動器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 379K |
| 代理商： | RF2705PCBA-41X |
5-128
RF2705
Rev A4 041026
Pin
22
Function
I SIG P
Description
In-phase I channel positive baseband input port.
Best performance is achieved when the ISIGP and ISIGN are driven
differentially with a 1.2V common mode DC voltage. The recom-
mended differential drive level (V
ISIGP
-V
ISIGN
) is 1.2V
P-P
for EDGE,
0.8V
P-P
W-CDMA modulation and 1.0V
P-P
for GMSK modulation.
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
Phase or amplitude errors between the ISIGP and ISIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the ISIGP and ISIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to can-
cel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
Common-mode noise on the ISIGP and ISIGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degrades sideband suppression.
In-phase I channel negative baseband input port. See pin 22.
Interface Schematic
23
24
I SIG N
MODE B
See pin 22.
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
CC
.
Ground for LO section, modular, biasing, variable gain amplifier, and
substrate.
See pin 6.
Pkg
Base
DIE FLAG
V
CC2
x1
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