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參數(shù)資料
| 型號(hào)： | RISC |
| 英文描述： | Unifying RISC and DSP |
| 中文描述： | 統(tǒng)一的RISC和DSP |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 176K |
| 代理商： | RISC |
Load-Store Architecture
The Hyperstone RISC technology is based on a load-
store architecture. It is register-oriented and built
around a 32-bit wide register stack that holds general-
purpose local registers and 26 global registers. Load
and store instructions are pipelined to a depth of 2
stages at the memory bus.
Global Registers
The global registers include a Program Counter, Status
Register, Stack Pointer, Upper Stack Bound, Bus Control
registers, Timer registers and 14 general-purpose
global registers.
Local Registers
The local registers are organized into a 64-word,
circular register stack to hold function/subroutine stack
frames. The stack crosses the register-memory
boundary. Organized into stack frames of up to 16
words, the current frames are kept on-chip and are
automatically pushed down to off-chip memory as
the register stack fills up. Likewise, as the frames are
popped off the stack, stack frames from memory are
automatically passed to the on-chip stack.
Register Stack with Overlapping Frames
The current stack frame can overlap with the previous
stack frame at a variable range to allow fast para-
meter passing. The overflow and underflow of the
register stack is managed automatically, relieving the
programmer of this task.
Variable-length instructions make program codes
more compact.
The basic size of a Hyperstone instruction is a 16-bit
halfword, however, the variable-length instructions
can have up to three 16-bit halfwords. As a result,
32-bit constants and 32-bit native addresses are
provided, thus making pre-instructions for generating
longer addresses or constants obsolete.
These variable-length instructions provide a program
code that is more compact compared to other RISC
and CISC architectures.
Technical Overview
Integrated Timers
The Hyperstone E1-32X has two hardware timers
integrated with a common time base and a resolution
of 1 μs.
The system timer is a general-purpose timer, which is
strongly supported by Hyperstone's real-time operating
system hyRTK. In combination with hyRTK, the
Hyperstone E1-32X provides up to 31 virtual timers
in stack-level tasks and up to 254 virtual timers in
interrupt-level tasks. Depending on the work load of
the CPU, the latency of these virtual timers is in the
range of 1..5 μs. Programming of these timers is very
easy because only the delay has to be defined. Very
important is that none of these timers generates any
overhead CPU cycles for pending time events. A
processing overhead of approximately 1 μs is required
only when a timer event occurs.
The other timer can be directly controlled by the user.
The signals of this timer are directly accessible at one
of the chip's I/O pins without any latency. It is
synchronized to the clock. Among others, this timer
is ideally suited for measuring pulse widths or
generation of pulse sequences.
Interrupts
Interrupts can be caused by external interrupt signals,
by the general-purpose timer interrupt, or by an I/O
Control Mode. Interrupts do not require a task switch.
An interrupt causes an interrupt-level task to be entered.
This interrupt-level task runs on the stack of the current
task executing, just a new stack frame is created.
Therefore, a full context switch is avoided. The interrupt
latency time is 0.1..0.2 μs when no other interrupt is
presently being served.
Up to 7 priority-controlled external interrupt signals
can be connected directly.
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