參數(shù)資料
型號(hào)： RM5270-200S
英文描述： 64-Bit Microprocessor
中文描述： 64位微處理器
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 387K
代理商： RM5270-200S
10
RM5271 Microprocessor, Document Rev. 1.3
Quantum Effect Devices
www.qedinc.com
If the
SysAD
carries data, then the
SysCmd
bus provides
information about the data (for example, this is the last data
word transmitted, or the data contains an error). The
SysCmd
bus is bidirectional to support both processor
requests and external requests to the RM5271. Processor
requests are initiated by the RM5271 and responded to by
an external device. External requests are issued by an
external device and require the RM5271 to respond.
The RM5271 supports one- to eight-byte transfers as well
as block transfers on the
SysAD
bus. In the case of a sub-
doubleword transfer, the three low-order address bits give
the byte address of the transfer, and the
SysCmd
bus indi-
cates the number of bytes being transferred.
Handshake Signals
There are six handshake signals on the system interface.
Two of these,
RdRdy*
and
WrRdy*
, are used by an exter-
nal device to indicate to the RM5271 whether it can accept
a new read or write transaction. The RM5271 samples
these signals before deasserting the address on read and
write requests.
ExtRqst*
and
Release*
are used to transfer control of the
SysAD
and
SysCmd
buses from the processor to an exter-
nal device. When an external device needs to control the
interface, it asserts
ExtRqst*
. The RM5271 responds by
asserting
Release*
to release the system interface to slave
state.
ValidOut*
and
ValidIn*
are used by the RM5271 and the
external device respectively to indicate that there is a valid
command or data on the
SysAD
and
SysCmd
buses. The
RM5271 asserts
ValidOut*
when it is driving these buses
with a valid command or data, and the external device
drives
ValidIn*
when it has control of the buses and is driv-
ing a valid command or data.
Non-overlapping System Interface
The RM5271 implements a non-overlapping system inter-
face, where only one processor request may be outstand-
ing at a time, and that the request must be serviced by an
external device before the RM5271 issues another request.
The RM5271 can issue read and write requests to an exter-
nal device, whereas an external device can issue null and
write requests to the RM5271.
For processor reads the RM5271 asserts
ValidOut*
and
simultaneously drives the address and read command on
the
SysAD
and
SysCmd
buses respectively. If the system
interface has
RdRdy*
asserted, then the processor
tristates its drivers and releases the system interface to the
slave state by asserting
Release*
. The external device can
then begin sending data to the RM5271.
Figure 7 shows a processor block read request and the
external agent read response for a system with no external
secondary cache. The read latency is 4 cycles (
ValidOut*
to
ValidIn*
), and the response data pattern is DDxxDD. Fig-
ure 8 shows a processor block write using write response
pattern DDxxDDxx (code 2 of the boot time mode select
options). This pattern indicates two data transfers back-to-
back, followed by two wait states. In the write case, there
may be secondary cache present.
Figure 7 Processor Block Read
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
Read
NData
NData
NData
NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
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