- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373294 > RM5271-200S 64-Bit Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | RM5271-200S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 387K |
| 代理商： | RM5271-200S |
12
RM5271 Microprocessor, Document Rev. 1.3
Quantum Effect Devices
www.qedinc.com
Int[5:0]*
,
NMI*
,
ExtReq*
,
Reset*
, and
ColdReset*
con-
tinue to operate in their normal fashion. If the
SysAD
bus is
not idle when the WAIT instruction completes the W pipe-
stage, then the WAIT is treated as a NOP until the bus
operation is completed. Once the processor is in Standby,
any interrupt, including the internally generated timer inter-
rupt, causes the processor to exit Standby mode and
resume operation where it left off. The WAIT instruction is
typically inserted in the idle loop of the operating system or
real time executive.
JTAG Interface
The RM5271 interface supports JTAG boundary scan in
conformance with the IEEE 1149.1 specification. The JTAG
interface is especially helpful for checking the integrity of
the processor’s pin connections.
Boot-Time Options
Fundamental operational modes for the processor are ini-
tialized by the boot-time mode control interface. This serial
interface operating at a very low frequency (
SysClock
divided by 256). The low frequency operation allows the ini-
tialization information to be kept in a low cost EPROM.
Alternatively, the mode stream bits could also be generated
by the system interface ASIC.
Immediately after the
VccOK
signal is asserted, the pro-
cessor reads a serial bit stream of 256 bits to initialize all
the fundamental operational modes.
ModeClock
run con-
tinuously from the assertion of
VccOK
.
Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit
0 is the first bit presented to the processor when
VccOK
is
de-asserted; bit 255 is the last in the mode bit stream.
Table 4:
Boot-Time Mode Bit Stream
Mode bit
0
Description
reserved (must be zero)
4:1
Write-back data rate
0: DDDD
1: DDxDDx
2: DDxxDDxx
3: DxDxDxDx
4: DDxxxDDxxx
5: DDxxxxDDxxxx
6: DxxDxxDxxDxx
7: DDxxxxxxDDxxxxxx
8: DxxxDxxxDxxxDxxx
9-15 reserved
7:5
SysClock to Pclock Multiplier
Mode Bit 20=0 / Mode Bit 20=1
0: Multiply by 2/x
1: Multiply by 3/x
2: Multiply by 4/x
3: Multiply by 5/2.5
4: Multiply by 6/x
5: Multiply by 7/3.5
6: Multiply by 8/x
7: Multiply by 9/4.5
8
Specifies byte ordering. Logically ORed with BigEn-
dian input signal.
0: Little endian
1: Big endian
10:9
Non-Block Write Control
00: R4000 compatible non-block writes
01: reserved
10: pipelined non-block writes
11: non-block write re-issue
11
Timer Interrupt Enable/Disable
0: Enable the timer interrupt on Int[5]
1: Disable the timer interrupt on Int[5]
12
Enable/Disable External Secondary Cache
0: Disable secondary cache
1: Enable secondary cache
14:13
Output driver strength - 100% = fastest
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
15
Select external secondary cache Pipeline Burst
SRAM type
0: Dual-cycle deselect
1: Single-cycle deselect
17:16
System configuration identifiers - software visible in
processor Config[21..20] register
19:18
Reserved: Must be zero
20
Select Sysclock to Pclock Multiply Mode
0: Integer Multipliers
1: Half-Integer Multipliers
21
External Bus Width
0: 64-bit
1: 32-bit
255:22
Reserved: Must be zero
Table 4:
Boot-Time Mode Bit Stream
Mode bit
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5271-225S | 64-Bit Microprocessor |
| RM5271-250S | 64-Bit Microprocessor |
| RM5271-266S | 64-Bit Microprocessor |
| RM5534T | Voltage-Feedback Operational Amplifier |
| RC5534AD | Voltage-Feedback Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5271-225S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-250S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-266S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-300S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-350S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。