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參數(shù)資料
| 型號： | RM5271-250S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 387K |
| 代理商： | RM5271-250S |
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
9
System Interface
The RM5271 provides a high-performance 64-bit multi-
plexed address/data system interface for optimum price/
performance. This interface is backward compatible with
the RM5270. However, unlike the RM5270 which provides
only an integral multiplication factor between
SysClock
and
the pipeline clock, the RM5271 allows half integral multipli-
ers, thereby providing greater granularity in the designers
choice of pipeline and system interface frequencies.
The system interface consists of a 64-bit Address/Data bus
with 8 parity bits and a 9-bit command bus. In addition,
there are 6 handshake signals and 6 interrupt inputs. The
interface is capable of transferring data between the pro-
cessor and memory at a peak rate of 1000MB/sec with a
125MHz SysClock.
Figure 6 shows a typical embedded system using the
RM5271. In this example, a bank of DRAMs, an optional
secondary cache, and a memory controller ASIC share the
processor’s
SysAD
bus while the memory controller pro-
vides separate ports to a boot ROM and an I/O system.
System Address/Data Bus
The 64-bit System Address Data (
SysAD[63:0]
) bus is
used to transfer addresses and data between the RM5271
and the rest of the system. It is protected with an 8-bit par-
ity check bus,
SysADC[7:0]
.
The system interface is configurable to allow easy interfac-
ing to memory and I/O systems of varying frequencies. The
data rate and the bus frequency at which the RM5271
transmits data to the system interface are programmable
via boot time mode control bits. The rate at which the pro-
cessor receives data is also fully controlled by the external
device.
System Command Bus
The RM5271 interface contains a 9-bit System Command
(
SysCmd[8:0]
) bus. The command bus indicates whether
the
SysAD
bus carries address or data information on a
per-clock basis. If the
SysAD
carries an address, then the
SysCmd
bus also indicates what type of transaction is to
take place (for example, a read or write).
Figure 6 Typical Embedded System Block Diagram
Table 3:
Cache Attributes
Characteristics
Instruction
Data
Secondary
Size
32KB
32KB
512K, 1M or
2M
Organization
2-way set
associative
2-way set
associative
direct
mapped
Replacement
Algorithm
Pseudo-LRU
Pseudo-LRU
direct
replacement
Line size
32B
32B
32B
Index
vAddr
11..0
vAddr
11..0
pAddr20..0
Tag
pAddr
31..12
pAddr
31..12
pAddr53..19
Write policy
n.a.
write-back/
write-through
block write-
through
Read order
sub-block
sub-block
sub-block
Write order
sequential
sequential
sequential
miss restart after
fetch of
entire line
first double
NA
Parity
per-word
per-byte
per-byte
Cache locking
set A
set A
none
RM5271
Memory I/O
Controller
DRAM
Flash/
Boot
Rom
Control
Address
x
x
72
PCI Bus
72
23
Latch
72
8
Secondary Cache
(optional)
MCM69T618
72
SysAD Bus
ScLine, etc.
SysCmd
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