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參數資料
| 型號： | RM5271-350S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數： | 11/24頁 |
| 文件大?。?/td> | 387K |
| 代理商： | RM5271-350S |
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
11
Figure 8 Processor Block Write
Enhanced Write Modes
The RM5271 implements two enhancements to the original
R4000 write mechanism: Write Reissue and Pipeline
Writes. The original R4000 allowed a write on the SysAD
bus every four SysClock cycles. Hence for a non-block
write, this meant that two out of every four cycles were wait
states.
Pipelined write mode eliminates these two wait states by
allowing the processor to drive a new write address onto
the bus immediately after the previous data cycle. This
allows for higher SysAD bus utilization. However, at high
frequencies the processor may drive a subsequent write
onto the bus prior to the time the external agent deasserts
WrRdy*
, indicating that it can not accept another write
cycle. This can cause the cycle to be aborted.
Write reissue mode is an enhancement to pipelined write
mode and allows the processor to reissue aborted write
cycles. If
WrRdy*
is deasserted during the issue phase of a
write operation, the cycle is aborted by the processor and
reissued at a later time.
In write reissue mode, a write rate of one write every two
bus cycles can be achieved. Pipelined writes have the
same two bus cycle write repeat rate, but can issue one
additional write following the deassertion of
WrRdy*
.
External Requests
The RM5271 can respond to certain requests issued by an
external device. These requests take one of two forms:
Write requests and Null requests. An external device exe-
cutes a write request when it wishes to update one of the
processors writable resources such as the internal interrupt
register. A null request is executed when the external
device wishes the processor to reassert ownership of the
processor external interface (the external device wants the
processor interface to go from slave state to master state).
Typically, a null request is executed after an external device,
that has acquired control of the processor interface via the
assertion of
ExtRqst*
, has completed a transaction
between itself and system memory in a system where
memory is connected directly to the
SysAD
bus. Normally,
this transaction would be a DMA read or write from the I/O
system.
Interrupt Handling
In order to provide better real time interrupt handling, the
RM5271 supports dedicated interrupt vectoring. When
enabled by the real time executive (by setting a bit in the
Cause register), interrupts vector to a specific address
which is not shared with any of the other exception types.
This capability eliminates the need to go through the nor-
mal software routine for exception decode and dispatch,
thereby lowering interrupt latency.
Standby Mode
The RM5271 provides a means to reduce the amount of
power consumed by the internal core when the CPU would
otherwise not be performing any useful operations. This
state is known as Standby Mode.
Executing the WAIT instruction enables interrupts and
causes the processor to enter Standby Mode. When the
wait instruction completes the W pipe stage, and if the
SysAD
bus is currently idle, the internal processor clocks
stop, thereby suspending the pipeline. The phase lock loop,
or PLL, internal timer/counter, and the “wake up” input pins:
SysClock
SysAD
Addr
Data0
Data1
Data2
Data3
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Write
NData
NData
NData
NEOD
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