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參數(shù)資料
| 型號： | RM7000-250S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級高速緩存數(shù)據(jù)發(fā)布 |
| 文件頁數(shù)： | 48/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-250S |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
48
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
10.3 System Interface Parameters
10.4 Boot-Time Interface Parameters
Parameter
1
Data Output
2,3
t
DO
Symbol Test Conditions
mode14..13 = 10 (fastest) 1.0
mode14..13 = 11
mode14..13 = 00
mode14..13 = 01
(slowest)
t
DS
t
rise
= see above table
t
fall
= see above table
t
DH
CPU Speed
200 MHz
Min Max
5.0
1.0
5.5
1.0
6.0
1.0
7.0
Units
ns
ns
ns
ns
250 MHz
Min
1.0
1.0
1.0
1.0
266 MHz
Min
1.0
1.0
1.0
1.0
300 MHz
Min
1.0
1.0
1.0
1.0
Max
5.0
5.5
6.0
6.5
Max
4.5
5.0
5.0
6.0
Max
4.5
4.5
5.0
5.5
Data Setup
4
2.5
2.5
2.5
2.5
ns
Data Hold
4
Notes
1.0
1.0
1.0
1.0
ns
1. Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O.
2. Capacitive load for all output timings is 50 pF.
3. Data Output timing applies to all signal pins whether tristate I/O or output only.
4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5. Only mode 14:13 = 10 is tested and guaranteed.
Parameter
7
Mode Data
Setup
Mode Data Hold t
DH
Symbol
t
DS
Test Condi-
tions
Min
4
Max
Units
SysClock cycles
0
SysClock cycles
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