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參數(shù)資料
| 型號(hào)： | RNA51A27FLP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO5 |
| 封裝： | SC-74A, SOT-23, MPAK-5 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | RNA51A27FLP |
RNA51xx Series
REJ03D0505-0200 Rev.2.00 Sep 13, 2007
Page 5 of 11
Electrical characteristics
(1) RNA51Axx Products
Temperature condition Ta = 25°C
Item
Symbol
Min
Typ
Max
Unit
Conditions
Supply voltage
VDD
1.1
5.5
V
pull-up resistor = 470 k
VOUT
≤ 0.1×VDD
Supply current
IDD
0.7
4.2
A
VDD = 5.5 V
Threshold voltage
–VTH
×0.99
–VTH
×1.01
V
Temperature coefficiency of the
thereshold voltage
(Reference value)
(–V
TH)
–VTH
Ta
±100
ppm/
°C
Ta = –40 to 85
°C
Threshold voltage hysteresis
VHYS
–VTH
×3%
–VTH
×5%
–VTH
×8%
V
0.2
1.2
VDD = 1.3 V
VOUT low-level output current
IOL
3.4
7.0
mA
VOUT = 0.5 V
VDD = 2.4 V
(–VTH
≥ 2.7 V)
VOUT Output leakage current
(open drain output)
ILEAK
0.1
A
VDD = VOUT = 5.5 V
Delay time
Note1
tDLY
10
20
35
ms
VDD = 1.1 to 5.5V, tTLH = 1
s
CD = 4.7 nF
MR Low-level input voltage
Note2
VIL
VDD
×0.25
V
MR High-level input voltage
VIH
VDD
×0.75
V
MR internal pull-up resistance
RMR
1
2
7
M
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Item
Symbol
Min
Typ
Max
Unit
Conditions
Supply voltage
VDD
1.1
5.5
V
pull-up resistor = 470 k
VOUT
≤ 0.1×VDD
Supply current
IDD
0.7
4.2
A
VDD = 5.5 V
Threshold voltage
–VTH
×0.99
–VTH
×1.01
V
Threshold voltage
temperature dependency
(Reference value for design)
(–V
TH)
–VTH
Ta
±100
ppm/
°C
Ta = –40 to 85°C
Threshold voltage hysteresis
VHYS
–VTH
×3%
–VTH
×5%
–VTH
×8%
V
0.2
1.2
VDD = 1.3 V
VOUT low-level output current
IOL
3.4
7.0
mA
VOUT = 0.5 V
VDD = 2.4 V
(–VTH
≥ 2.7 V)
–1.4
–2.7
VDD = 4.5 V
(–VTH
≤ 4.0 V)
VOUT High-level output current
(CMOS output)
IOH
–1.5
–3.0
mA
VOUT =
VDD–0.5 V
VDD = 5.5 V
Delay time
Note1
tDLY
10
20
35
ms
VDD = 1.1 to 5.5 V, tTLH = 1
s
CD = 4.7 nF
MR Low-level input voltage
Note2
VIL
VDD
×0.25
V
MR High-level input voltage
VIH
VDD
×0.75
V
MR internal pull-up resistance
RMR
1
2
7
M
Note:
1.
Delay time is specified when charging starts in the condition that CD pin is completely discharged. When discharging of CD
pin is not complete because of immediate stop and other reasons, the delay time is not guaranteed. Therefore, when
passing of VDD pin input voltage immediately stops (the period of condition that VDD pin input voltage is lower than the
detected voltage is short), discharging of external capacitor CD is inadequate, and the delay time becomes much shorter
than the minimum guaranteed value. Be sure to fully check that there are no problems as the system.
2.
Minimum value of low-pulse width to be input to MR pin depends on the value of external capacitor CD. Therefore, set the
low-pulse width to be input to MR pin to the minimum input low-pulse width shown in figure 1 or more.
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