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參數資料
| 型號： | RNA51A30FLPEL |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO5 |
| 封裝： | SC-74A, SOT-23, 5 PIN |
| 文件頁數： | 9/12頁 |
| 文件大小： | 148K |
| 代理商： | RNA51A30FLPEL |
RNA51xx Series
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 6 of 11
1
10
100
1000
0.1
1
10
100
1000
External Capacitor CD (nF)
MR
pin
minimum
input
low
pulse
width
(
s)
Figure 1 Dependence of MR pin minimum input low pulse width and external capacitor CD
Pin Description
PIN
NAME
FUNCTION
1
VOUT
VOUT changes from high to low whenever VDD drops below –V
TH.
A pull-up resistor from 470 k
to 1 M should be used on this pin for open-drain output.
2
VDD
Supply voltage and input for voltage detector.
A decoupling capacitor with excellent high frequency characteristics should be placed near VDD
pin and connected between VDD and GND pin.
3
GND
Ground
4
MR
Active-low Manual Reset Input.
VOUT is low-level while MR is low.
Once MR is disabling,
VOUT turn to high-level after delay time.
MR pin is internally pulled up to VDD through 2 M
.
5
CD
Connect capacitor between CD and GND pin to set programmable delay time.
Ceramic capacitor from 100 pF to 0.1
F is recommended.
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