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參數(shù)資料
| 型號(hào)： | RP-21005D2-820Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, DMA10 |
| 封裝： | DIP-10 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 86K |
| 代理商： | RP-21005D2-820Q |
7
SSPC. Therefore the case, POWER IN, and Control Circuit are
all electrically isolated. FIGURE 1 shows this isolation as the
"ISOLATED CONTROL CIRCUIT."
The electrical isolation is supported by an internal power oscilla-
tor that electrically isolates separate internal power supplies that
will power the internal analog and digital monolithics. This isola-
tion prevents load or logic ground loops from affecting the prop-
er operation of the SSPC. The isolation also insures that a fault
of the switch (MOSFET) could never propagate back into the
SSPC logic or cause damage to the logic side.
SSPC failure or Status 2 shorted to ground
LOW
HIGH
LOW
Load is “OFF”, Normal Condition
HIGH
LOW
SSPC failure or Status 2 shorted to ground
LOW
HIGH
Load is “ON”, Normal Condition
HIGH
LOW
HIGH
Load is “OFF”, Tripped
LOW
HIGH
Load is “ON”, Load < 5.0% Rated Current
HIGH
SSPC failure or Status1 shorted to ground
HIGH
LOW
SSPC failure, or Status1 and Status 2 short-
ed to ground, or No Bias
LOW
SYSTEM STATUS
STATUS 2
LOW
STATUS 1
CONTROL
TABLE 6. OPTIONAL STATUS TRUTH TABLE
Status 1 indicates a logic LOW if > 15% of the rated current is flowing.
Status 2 indicates a logic LOW if the SSPC is tripped due to overcurrent.
OPTIONS
The Following characteristics can be factory modified on special
orders:
I2T TRIP CURVE: K-factor adjustments
OUTPUT RISE AND FALL TIMES: Turn-off and Turn-on times
can be factory modified (e.g., capacitive loads)
CURRENT RANGE
POWER-ON RESET: Other options are available
INPUT CONTROL:
TTL or CMOS or Both with Hysteresis (Schmitt trigger char-
acteristics)
CUSTOM PACKAGING
OPTIONAL STATUS TRUTH TABLE (See TABLE 6)
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