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參數(shù)資料
| 型號(hào)： | RP-21015D1-360Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, DMA10 |
| 封裝： | DIP-10 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 86K |
| 代理商： | RP-21015D1-360Q |
3
FUNCTIONAL DESCRIPTION
The RP-21000 series of Solid-State Power Controllers incorpo-
rate the wire protection feature of electromechanical circuit
breakers and the reliability of solid-state relays. In addition to the
solid-state relay's input logic compatibility, the RP-21000 series
provide logic compatible status outputs.
A TTL/CMOS compatible input provides external control of the
power switch's "ON/OFF" state. A logic high on this control input
turns the power to the load "on." A logic low will turn the power
switch off, which removes power from the load.
In the event of an overload the RP-21000 series will trip, just like
a circuit breaker, and automatically remove power from the load.
In order to turn back on the control input must be brought to a
logic low, and then returned to a logic high state.
As in a circuit breaker, the SSPC’s time to trip depends on the
current level.
Slight overloads will cause longer trip times.
Heavy overloads will cause shorter trip times. The fault ("Instant
Trip") and I2T trip curve (see FIGURE 2) shows the trip time as
a function of current for a single trip or repetitive trips with at least
10 seconds between trip and turn on. Attempts to repeatedly
turn on into an overload will result in the thermal memory short-
ening each trip time. This "memory" protects the wire, load and
Solid-State Power Controller.
The status lines are TTL/CMOS compatible outputs which reflect
the state of the SSPC, the load, and the Built-In-Test (BIT) cir-
cuits. The status permits an external subsystem to monitor and
ultimately control the SSPC. TABLE 5 defines the status lines'
states which indicate the various states of the SSPC. Further
explanation of the status lines appears in the applications infor-
mation section.
The RP-21000 series SSPCs are characterized by their current
rating and maximum "on" resistance listed in TABLE 4. These
parameters are established by the number of Power FETs
placed in parallel within the SSPC.
The trip function is implemented by two separate circuits, a true
I2T trip comparator and a short circuit fault comparator. They are
independent of each other but work together to protect the sys-
tem.
If the load current is less than 110% of rated current, the SSPC
will never trip. If the load current is greater than 145%, the SSPC
will always trip.
For load currents less than 800%, the trip time can be found from
FIGURE 2 by drawing a horizontal line on FIGURE 2 at the cur-
rent level of interest.
The SSPC will always trip at a time
between the two curves. This is true I2T tripping.
When the SSPC trips in accordance with the I2T characteristics,
the fall time is 200 s, maximum.
For load currents greater than 1200%, the SSPC will turn off in
less than 25 s. Between 800% and 1200%, the SSPC will turn
off in a time less than the "max. trip limit" shown in FIGURE 2
and may turn off in less than 25
s. When the SSPC turns off
under these fault conditions, the fall time is less than 25 s.
10,000
1,200
1,000
800
600
400
200
0
10
1.0
0.1
0.01
0.001
s
25
145%
110%
LOA
D
CUR
RE
NT
%
I-
MAX
TIME- SECONDS
AL
WAYS TRIP
NEVE
R TRIP
MAX. TRIP LIMIT
INSTANT
TRIP
MIN. TRIP LIMIT
FIGURE 2. TRIP CHARACTERISTICS
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