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參數(shù)資料
| 型號： | RSC-412864LQFP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Speech Recognition Processor |
| 中文描述： | 語音識別處理器 |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | RSC-412864LQFP |
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RSC-4128
Data Sheet
If an “irq” bit is set high and the corresponding “imr” bit is set high and the Global Interrupt Enable (“gie”; register
FF.bit0) bit is set high, an interrupt will occur. Interrupts may be nested if software handles saving and restoring the
“flagsHold” register (register CF). The “flags” register is copied to the “flagsHold” register and then the Global
Interrupt Enable is cleared, preventing subsequent interrupts until the IRET instruction is executed. The IRET
instruction will restore the “flags” register from the “flagsHold” register. The Global Interrupt Enable bit in the “flags”
register must not be re-enabled during the period after an interrupt has been acknowledged and before an IRET
instruction has been executed unless interrupt nesting is desired.
If an interrupt occurs during an instruction that clears the Global Interrupt Enable bit (typically the CLI instruction)
the value of the “gie” bit will be 0 upon completion of the Interrupt Service Routine and Return From Interrupt to the
instruction following the one that cleared the “gie” bit. (NOTE: This is a change from the operation of the RSC-364.)
The “flagsHold” register is accessible under program control at address CF in order to improve multi-tasking
operation.
External interrupts may be enabled on pins P0.0 (1
st
external interrupt request) and P0.2 (2
nd
external interrupt
request), by setting register FD.Bit3=1 and register FD.Bit6=1, respectively. The polarity of the edges to trigger an
external interrupt request for P0.0 and are controlled by register D5.Bits[1:0]. Setting D5.Bit0=0 will cause a
positive going edge on P0.0 to generate and interrupt and D5.Bit0=1 will cause a negative going edge to generate
an interrupt. The same controls for P0.2 are possible with D5.Bit1. The corresponding external “irq” flag will be set
if the transition matches the interrupt edge control bit.
NOTE: If P0.0 or P0.2 are configured as outputs, writing to those outputs can trigger external interrupt requests if
the proper edge polarities occur. The user must be careful to avoid this, unless it is intended to use this as a way of
generating interrupt requests under internal software control.
An interrupt is disabled by writing a zero to the corresponding bit in the imr register (register 0FDH). However, an
active interrupt request can still be pending. To be certain that an interrupt does not happen, you should clear the
interrupt request flag in the irq register (register 0FEH) as well. For example:
; Disable timer 1 interrupt
cli
and
imr,#0FEH
; mask new interrupt requests
mov
irq,#0FEH
; clear any pending interrupt request
sti
For each interrupt, execution begins at a different address:
Interrupt #0
Address 04H
(Overflow of Timer 1)
Interrupt #1
Address 08H
(Overflow of Timer 2)
Interrupt #2
Address 0CH
(Filter End Marker)(Reserved for Technology code)
Interrupt #3
Address 10H
(Edge of P00)
Interrupt #4
Address 14H
(Overflow of Timer 3)
Interrupt #5
Address 18H
(Block End)(Reserved for Technology code)
Interrupt#6
Address 1CH
(Edge of P02)
Interrupt#7
Address 20H
(Overflow of MT timer)
The interrupt vector is generated as a 20-bit address. The low 16 bits are derived from the execution table above,
and the high 4 bits are selected as a normal code fetch as described in the “Memory Addressing” section.
Specifically, the “cb1” bit is not touched by the interrupt.
If the corresponding mask register bit is clear, the “irq” bit will not cause an interrupt. However, it can be polled by
reading the “irq” register.
24
P/N 80-0206-J
2004 Sensory Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RSC4128 | Speech Recognition Processor |
| RT1A3906 | |
| RT1N44BC | TRANSISTOR |
| RT1N44BM | TRANSISTOR |
| RT1N44BS | TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| RSC-4128DIE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Speech Recognition Processor |
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