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參數(shù)資料
| 型號： | RSC4128 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Speech Recognition Processor |
| 中文描述： | 語音識別處理器 |
| 文件頁數(shù)： | 17/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | RSC4128 |
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Data Sheet
RSC-4128
The –RDR signal goes low when the –XM pin is held low and
either
1) the chip executes an instruction fetch,
or
2) the chip executes a
MOVC
read instruction,
or
3) the chip executes a
MOVX
read instruction
and
the “rw” bit is zero.
This active low signal is used to enable an external ROM or other external memory containing both executable
code and fixed, read-only data.
The –RDF signal goes low when the chip executes a
MOVX
read instruction and the “rw” bit is set to 1. This active
low signal is used to read an external flash or other external memory that is used solely for the purpose of Data
Space, either read-only fixed data or read-write dynamic data.
The –WRD signal goes low when the processor executes a
MOVX
write instruction. The –WRC signal goes low
when the processor executes a
MOVC
write instruction. These signals do not depend on the contents of the
Extended Address Register or the –XM signal, since a write by definition cannot be done to internal ROM.
External Memory Interface during Powerdown
The external memory interface (A[19:0], D[7:0], -RDR, -WRC, -RDF and –WRD) automatically goes into a high-Z
state and is pulled up by a 100 Kohm internal resistor when the “pdn” bit is set, to conserve current.
One output, PDN, is active high when RSC-4128 is powered-down. This pin can be connected to the (active low)
chip enable pins of external memory devices to reduce power consumption during RSC-4128 power-down.
Wait States
17
P/N 80-0206-J
2004 Sensory Inc.
General control of wait states is managed by register FC.Bits[7:5] (“bank” register). These bits are set to a value of
7 on reset, defaulting to slower memory. An initialization routine may be used to configure for faster memory.
Access of external ROM space is always controlled by these wait state bits. Internal ROM space and all external
R/W space accesses may also controlled by these bits, unless otherwise selected by bits in the clock extension
register (register D6, “clkExt”) The internal RAMs always operate with zero wait states.
Register D6 provides for extended control of some clocks derived from OSC1 for producing additional timer scaling
or specialized wait states. When Bit 5 is set, it overrides the “bank” register control of wait states during
MOVX
instructions which access external read/write memory (register D2.Bit4=1), and forces a fixed value of 4 wait states
(nominal 350ns access). When Bit 7 is set, it overrides the “bank” register control of wait states during internal
ROM accesses and forces zero wait states. Using these controls, various memory access speeds may be
accommodated within one application.
Bit 5
0: Certain
MOVX
* instructions use the Wait State divisor in register FC.Bits[7:5]
1:Certain
MOVX
* use fixed 4 Wait States (nominal 350nsec access)
Cleared by reset
Bit 6
0: MT timer clock is disabled
1: MT timer clock I s enabled
Cleared by reset
Bit 7
0: Accesses to internal ROM use the Wait State divisor set in register 0FCh[7:5]
1: Accesses to internal ROM use selected CLK (no wait states)
Cleared by reset.
*
MOVX
accessing external read-write memory (“rw”; register D2.Bit4=1).
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