
92
Real time clock module
CS
0
t
RC
t
ACC
t
ACS
t
CLZ
t
OLZ
t
OHZ
t
CHZ
t
CHZ
t
OH
t
ACS
t
CLZ
t
ARD
CS
1
RD
A
0
to A
3
D
0
to D
3
!!
CS
0
t
WC
t
AW
t
CW
t
AS
t
DW
t
DH
t
WR
CS
1
WR
A
0
to A
3
D
0
to D
3
CS
0
t
wC
t
AW
t
AS
t
DW
t
DH
t
WR
CS
1
WR
A
0
to A
3
D
0
to D
3
t
WP
BUS
INTERFACE
CIRCUIT
FOUT CONTROLLER
Temperature
Sensor
DIVIDER
F
OUT
F
CON
*2
VTEMP
IRQ
A
0
to A
3
D
0
to D
3
WR
*This is a block diagram for RTC-7301SF.
Be aware that RTC-7301DG differs according to the following 2 points.
*1)The VTEMP output is not connected to an external pin.
*2)
The FCON input pin is not connected to an external pin, but is fixed at "H" internally.
RD
CS0
CS1
7301SF
*1
*1
7301DG
Degital Trimming
REGISTER
CLOCK and CALENDAR
TIMER REGISTER
ALARM REGISTER
CONTROL REGISTER
and
SYSTEM CONTROLLER
INTERRUPTS
CONTROLLER
OSC
32.768 kHz
Control line
GND=0 V, Ta= -40
°
C to + 85
°
C Input conditions: VI= 0.5 x VDD, VO= 0.5 x V
DD
Output load: CL= 100 pF (tACC,tACS,tARD)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
F
OS
8
o
8
o
o
8
o
8
o
8
80
800
TEST
Bank Sel 1
4
40
4
40
4
o
4
4
o
4
o
4
40
400
TEMP
Bank Sel 0
2
20
2
20
2
20
2
2
20
2
o
2
20
200
2000
STOP
1
10
1
10
1
10
1
1
10
1
10
1
10
100
1000
BUSY/ADJ
1 second digit
10 second digit
1 minute digit
10 minute digit
1hour digit
10 hour digit
Day digit
1 day digit
10 day digit
1 month digit
10 month digit
1 year digit
10 year digit
100 year digit
1000 year digit
Control registers
Item
Read cycle time
Address access time
CE access time
RD access time
CE output set time
CE output floating
RD output set time
RD output floating
Output hold time
Write cycle time
Chip select time
Address valid end of write
Address setup time
Address hold time
Write pulse width
Input data set time
Input data hold time
FOUT output frequency duty
Symbol
t
RC
t
ACC
t
ACS
t
ARD
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
OH
t
WC
t
CW
t
AW
t
AS
t
WR
t
WP
t
DW
t
DH
DUTY
Condition
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FOUT=
32.768 kHz
Unit
n
s
n
s
n
s
n
s
n
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Min.
150
—
—
—
5
—
5
—
10
150
140
140
0
0
130
80
0
40
Max.
—
150
150
100
—
60
—
60
—
—
—
—
—
—
—
—
—
60
Max.
—
85
85
45
—
30
—
30
—
—
—
—
—
—
—
—
—
60
Min.
85
—
—
—
3
—
3
—
5
85
70
70
0
0
65
35
0
40
A
b
b
b
b
Register
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
AE
8
AE
8
AE
AE
8
AE
CTEMP
o
FE
TEST
Bank Sel 1
4
40
4
40
4
4
4
CDT_ON
FD2
o
TEMP
Bank Sel 0
2
20
2
20
2
20
2
2
20
FD1
FD4
AF
STOP
1
10
1
10
1
10
1
1
10
FD0
FD3
AIE
BUSY/ADJ
1 second digit
10 second digit
1 minute digit
10 minute digit
1hour digit
10 hour digit
Day digit
1 day digit
10 day digit
—
—
CS1 Controller
FOUT divider ratio setting register
FOUT divider ratio setting register
Alarm control
Control register
A
b
b
b
b
Register
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DT3
DT_ON
o
o
8
128
8
128
TE
o
o
o
o
o
TEST
Bank Sel 1
DT2
DT6
o
o
4
64
4
64
TI/TP
o
o
o
o
o
TEMP
Bank Sel 0
DT1
DT5
o
o
2
32
2
32
TD1
o
o
o
o
o
TF
STOP
DT0
DT4
o
o
1
16
1
16
TD0
o
o
o
o
o
TIE
BUSY/ADJ
Digital offset
—
—
Timer counter
preset value
Timer counter
data
Timer settings
—
—
—
—
—
Timer control
Control register
A
b
b
b
b
Registers
V
DD
=2.4 to 3.6 V V
DD
=4.5 to 5.5 V