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參數(shù)資料
| 型號： | RTH010DIE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 9GHz Bandwidth 1GS/s Dual Track-and-Hold |
| 中文描述： | 9GHz帶寬個GS / s的雙跟蹤和保持 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 712K |
| 代理商： | RTH010DIE |
RTH010 DATA SHEET REV F
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page
3
Electrical Specification (Continued)
PARAMETER
TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH1
Aperture Delay
Aperture Jitter
SYMBOL
CONDITIONS, NOTE
TEST LEVEL
MIN
TYP
MAX
UNITS
ta
t
After V(CLK1) - V(CLK1B) Goes Neg.
Jitter Free 1-GHz 0.5-Vpp CLK1(B)
4,5
At Hold Capacitors. ttrack1,min
Observed
Per Sqrt(Hold Time)
50% Duty Cycle Clock
50% Duty Cycle Clock
4
3
+60
100
ps
fs
70
130
Settling Time to 1 mV
ts
4
300
ps
Differential Pedestal/V
IN
Diff. Droop Rate/V
IN
Hold Noise
7
Minimum CLK1 Freq.
Maximum CLK1 Freq.
Maximum Hold Time
8
HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH1
Acquisition Time to 1 mV
9
Max. Acq. Slew Rate
Rise Time
9
Minimum Track Time
6
4
4
4
2
2
3
-2
-1
50
8
%
%/ns
μ
V/
√
ns
MHz
MHz
ns
fclk1, min
fclk1, max
thold1, max
200
1250
12
1000
5
tacq
dvdt,max
tr
ttrack1,min
At Hold Caps, FSR Step At Input
At Hold Caps, FSR Step At Input
20 – 80%
thold1,max Observed
Required Accumulated Track Time
After thold1,max Violation
4
4
3
2
250
15
0.4
ps
V/ns
ps
ns
50
Recovery Time
3
4
ns
TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH2
Aperture Delay
Settling Time to 1 mV
10
Differential Pedestal/V
IN
Diff. Droop Rate/V
IN
Hold Noise
7
Minimum CLK2 Freq.
Maximum CLK2 Freq.
Maximum Hold Time
8
HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH2
Minimum Track Time after
TH1 in Hold Mode
ta2
ts2
After V(CLK2) - V(CLK2B) Goes Neg.
At DTH Output. ttrack2,min Observed
Per Sqrt(Hold Time)
50% Duty Cycle Clock
50% Duty Cycle Clock
4
4
4
4
4
2
2
3
+60
300
±0.25
-0.12
25
15
ps
ps
%
%/ns
μ
V/
√
ns
MHz
MHz
ns
11
fclk2,min
fclk2,max
thold2,max
100
1250
20
1000
10
ttrack2,min
thold2,max Observed
2
0.5
ns
Recovery Time
Required Accumulated Track Time
After thold2,max Violation
3
4
ns
POWER SUPPLY REQUIREMENTS
Positive Supply Voltage
VCC Current
Negative Supply Voltage
VEE Current
Power Dissipation
Warm-up Time
VCC
ICC
VEE
IEE
After Power-up
1
1
1
1
1
2
4.75
-5.45
2.2
5.0
130
-5.2
325
2.35
5.25
180
-4.95
400
2.5
10
V
mA
V
mA
W
s
4
The clock source jitter and the aperture jitter combine in an rms manner to yield the total sampling jitter. See Definition of Terms.
5
Device aperture jitter increases as the V(CLK1) – V(CLK1B) slew rate at the zero crossing decreases. See Theory of Operation.
6
The differential pedestal error is proportional to the input signal. For TH1 it corresponds to a track-to-hold gain ~ -0.17 dB. This
gain loss may be observed at the DTH output if TH2 is in track mode during the TH1 track-to-hold transition.
7
The variance of the hold noise is proportional to the hold time, thold. For example, for TH1, a 4-ns hold time, thold1, gives about
100
μ
V accumulated hold noise. TH1 and TH2 hold noise, up to the output sampling instant, should be rms added to the hold
mode integrated noise of the DTH.
8
Maximum hold time is determined by droop of single-ended hold capacitor voltages. The resulting shift of internal operating
voltages is not directly observable at the DTH outputs but eventually causes device performance degradation.
9
TH1 tacq, dvdt,max, and tr also apply to the reconstructed DTH output if sub-sampling a fast-edge repetitive wave form.
10
Output is settled ta2 + ts2 after CLK2(B) downward transition.
11
The differential pedestal error is proportional to the input signal. For TH2 it corresponds to a track-to-hold gain ~ ±0.02 dB.
12
ttrack2,min > ts, since the buffered TH1 output onto the TH2 hold capacitors lags behind the TH1 hold capacitor signal.
13
The part functions immediately and reaches specification after warm-up time.
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