參數(shù)資料
型號： RTL8130
廠商： Electronic Theatre Controls, Inc.
英文描述： REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 瑞昱單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 15/58頁
文件大?。?/td> 657K
代理商： RTL8130
RTL8100B(L)
2001-11-9
Rev.1.41
15
5.5 Interrupt Mask Register
(Offset 003Ch-003Dh, R/W)
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset will clear all mask
bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to cause an interrupt. The Interrupt Status
Register bits are always set to 1 if the condition is present, regardless of the state of the corresponding mask bit.
Bit
15
R/W
R/W
Symbol
SERR
Description
System Error Interrupt:
1 => Enable, 0 => Disable.
14
13
12-7
6
5
R/W
R/W
-
R/W
R/W
TimeOut
LenChg
-
FOVW
PUN/LinkChg
Time Out Interrupt:
1 => Enable, 0 => Disable.
Cable Length Change Interrupt:
1 => Enable, 0 => Disable.
Reserved
Rx FIFO Overflow Interrupt:
1 => Enable, 0 => Disable.
Packet Underrun/Link Change Interrupt:
1 => Enable, 0 =>
Disable.
Rx Buffer Overflow Interrupt:
1 => Enable, 0 => Disable.
Transmit Error Interrupt:
1 => Enable, 0 => Disable.
Transmit OK Interrupt:
1 => Enable, 0 => Disable.
Receive Error Interrupt:
1 => Enable, 0 => Disable.
Receive OK Interrupt:
1 => Enable, 0 => Disable.
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
RXOVW
TER
TOK
RER
ROK
5.6 Interrupt Status Register
(Offset 003Eh-003Fh, R/W)
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt
Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this
register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the
corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
Bit
15
R/W
R/W
Symbol
SERR
Description
System Error:
Set to 1 when the RTL8100B(L) signals a system error
on the PCI bus.
Time Out:
Set to 1 when the TCTR register reaches to the value of the
TimerInt register.
Cable Length Change:
Cable length is changed after Receiver is
enabled.
Reserved
Rx FIFO Overflow:
Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change:
Set to 1 when CAPR is written but
Rx buffer is empty, or when link status is changed.
Rx Buffer Overflow:
Set when receive (Rx) buffer ring storage
resources have been exhausted.
Transmit (Tx) Error:
Indicates that a packet transmission was
aborted, due to excessive collisions, according to the TXRR's setting.
Transmit (Tx) OK:
Indicates that a packet transmission is completed
successfully.
Receive (Rx) Error:
Indicates that a packet has either CRC error or
frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.
Receive (Rx) OK:
In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.
14
R/W
TimeOut
13
R/W
LenChg
12 - 7
6
5
-
-
R/W
R/W
FOVW
PUN/LinkChg
4
R/W
RXOVW
3
R/W
TER
2
R/W
TOK
1
R/W
RER
0
R/W
ROK
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