參數(shù)資料
型號: S-812C26AY-Z
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: 2.6 V FIXED POSITIVE LDO REGULATOR, 0.68 V DROPOUT, PBCY3
封裝: TO-92, 3 PIN
文件頁數(shù): 10/49頁
文件大?。?/td> 873K
代理商: S-812C26AY-Z
HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR
S-812C Series
Rev.2.0_01
18
Seiko Instruments Inc.
Precautions
Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low. When
mounting an output capacitor between the VOUT and VSS pins (CL) and a capacitor for stabilizing the
input between VIN and VSS pins (CIN), the distance from the capacitors to these pins should be as short
as possible.
Note that output voltage may be increased at low load current of less than 1 A.
At low load current less than 100A output voltage may increase when the regulating operation is halted
by the ON/OFF pin.
To prevent oscillation, it is recommended to use the external parts under the following conditions.
Equivalent Series Resistance (ESR): 10
or less
Input series resistance (RIN):
10
or less
A voltage regulator may oscillate when power source impedance is high and input capacitor is low or not
connected.
Pay attention to the operating conditions for input/output voltage and load current so that the power loss in
the IC does not exceed the power dissipation of the package.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
相關PDF資料
PDF描述
S-812C28AY-B 2.8 V FIXED POSITIVE LDO REGULATOR, 0.68 V DROPOUT, PBCY3
S-812C44AUA-C2Y-T2 4.4 V FIXED POSITIVE LDO REGULATOR, 0.3 V DROPOUT, PSSO3
S-812C47AUA-C3B-T2 4.7 V FIXED POSITIVE LDO REGULATOR, 0.27 V DROPOUT, PSSO3
S-812C51AY-B 5.1 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PBCY3
S-812C53AMC-C3H-T2 5.3 V FIXED POSITIVE LDO REGULATOR, 0.25 V DROPOUT, PDSO5
相關代理商/技術參數(shù)
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