參數(shù)資料
型號： S12EETS2KV1D
廠商： Motorola, Inc.
英文描述： MC9S12DT128 Device User Guide V02.09
中文描述： MC9S12DT128設(shè)備的用戶手冊V02.09
文件頁數(shù)： 125/138頁
文件大?。?/td> 2083K
代理商： S12EETS2KV1D
MC9S12DT128 Device User Guide — V02.09
125
A.7 SPI
A.7.1 Master Mode
Figure A-5
and
Figure A-6
illustrate the master mode timing. Timing values are shown in
Table A-18
.
SS
1
(OUTPUT)
Figure A-5 SPI Master Timing (CPHA = 0)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
9
5
6
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
10
4
4
2
9
(CPOL
=
0)
(CPOL
=
1)
3
11
12
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
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