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參數(shù)資料
| 型號(hào)： | S1519BGAJ-FREQ2 |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | VCXO, CLOCK, 50 MHz - 125 MHz, HCMOS/TTL OUTPUT |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 144K |
| 代理商： | S1519BGAJ-FREQ2 |
SaRonix
S1310 / S1510 Series
SaRonix
Voltage Controlled Crystal Oscillator
Technical Data
3.3 & 5V, HCMOS
141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
DS-162 REV D
5.2.2
All specifications are subject to change without notice.
Package Details
Part Numbering Guide
5.08
.46±.08
.018±.003
0.91
7.62±.20
.300±.008
120°
120°
120°
7.62±.20
.300±.008
1.5
.059
Pin 5
Output
Pin 8
V
DD
Pin 1
Control Voltage
Pin 4
GND Case (V
SS
)
Scale: None (Dimensions in inches
SARONIX
Denotes Pin 1
Pin 3 Input
Logic 1 or NC
Logic 0 or GND
Pin 8 Output
Oscillation
High Impedance
Required Input Levels on Pin 3:
Logic 1 = 3.0 V min
Logic 0 = 0.3V max
S T 151 0 A A B J - 60.0000
SaRonix
Frequency (MHz)
T
= Tri-State
optional: full size 3.3 or 5V
standard: 1/2 size 5V
not available: 1/2 size 3.3V
Blank
= Non Tri-State
Linearity
A = 5%
B = 10%
POWER
SUPPLY
HALF SIZE PACKAGE
SARONIX
VCXO
Denotes Pin 1
12.2±.13
.480±.005
Pin 3
Pin 1
Pin 7
4.57±.13
.18±.005
7.62±.13
.300±.005
Pin 12
Pin 14
15.24±.13
.600±.005
5.08
4.85±.25
.191±.01
3.94±.25
.155±.010
.46±.05
.018±.002
FULL SIZE PACKAGE
21.0
CONTROL VOLTAGE
C
L
= 30pF or 50pF
(Note A)
GND
OSCILLATOR
V
DD
OUT
Pin 7 (4)
Pin 14 (8)
Pin 8 (5)
Pin 1 (1)
*
mA
M
V M
CONTROL VOLTAGE
NOTE A: CL includes probe and fixture capacitance
*
( ) Indicates pin numbers for half size package
Figure 2
–
TTL load Test Circuit
Pin 14 (8)
Pin 8 (5)
Pin 1 (1)
*
Pin 7 (4)
OSCILLATOR
N/C
GND
OUT
V
DD
V M
mA
M
POWER
SUPPLY
C
L
= 15pF
(Note A)
MMDB7000
or Equiv
R
L
= 780
Pullability (minimum APR)
A = ±50 ppm
B = ±100 ppm
G = ±25 ppm
H = ±75 ppm
TEST
POINT
TEST
POINT
A = ±25 ppm, 0 to 70
°
C
B = ±50 ppm, 0 to 70
°
C
E = ±50 ppm, -40 to +85
°
C
Stability Tolerance
Series
131 = 3.3V, HCMOS/TTL VCXO
151 = 5V, HCMOS/TTL VCXO
Model
0 = Full size package
9 = Half size package
NOTE A: C
L
includes probe and fixture capacitance (50pF max 32 to 50 MHz, 30pF max 50+ to 125 MHz)
*
( ) Indicates pin numbers for half size package
Figure 1
–
30pF or 50pF load Test Circuit
0.91
.036
13.0
.510
max
Tri-State Logic Table
Test Circuits
(4) Glass
Insulators
Pin 8
Pin Function:
Pin 1: Control Voltage
Pin 3: Tri-State control
(Tri-State version only)
Pin 7: GND / Case (V
SS
)
Standard Marking Format
Includes Date Code, Frequency & Model
Pin 8: Output
Pin 12: N/C
(Tri-State version only)
Pin 14: VDC (V
DD
)
13.0
10.87
.428
max
6.86
.270
13.0
.510
max
6.0
.236
1.5
.059
Standard Marking Format
Includes Date Code, Frequency & Model
Lead Style
Blank = Thru-Hole
J = Gull Wing
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