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參數(shù)資料
| 型號： | S1C6N3B0D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC54 |
| 封裝： | DIE-54 |
| 文件頁數(shù)： | 51/79頁 |
| 文件大小： | 606K |
| 代理商： | S1C6N3B0D0A0100 |
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S1C6N3B0 TECHNICAL MANUAL
EPSON
47
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Serial Interface)
4.9.3 Master mode and slave mode
The serial interface of the S1C6N3B0 Series has two types of operation mode: master mode and slave
mode.
In the master mode, it uses an internal clock as the synchronous clock of the built-in shift register and
outputs this internal clock to the SCLK terminal to control the external (slave side) serial interface.
In the slave mode, the synchronous clock output from the external (master side) serial device is input
from the SCLK terminal and is used as the synchronous clock to the built-in shift register. Furthermore
the SRDY signal that indicates whether the serial interface is in ready status or not is output from the
SRDY terminal (when the SRDY terminal is set).
The master mode or slave mode is selected using the SCS0 and SCS1 registers; when the master mode is
selected, a synchronous clock may be selected from among 2 types as shown in Table 4.9.3.1.
Table 4.9.3.1 Synchronous clock selection
SCS1
1
0
SCS0
1
0
1
0
Mode
Master mode
–
Slave mode
Synchronous clock
CLK/2
CLK
–
External clock
CLK:
CPU system clock fosc
CLK/2: CLK divided by 2
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as
follows:
In the master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically
suspended.
In the slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked.
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