
S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-31
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) I/O Memory map (00FF00H–00FF02H, MPU mode)
Note:
All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
Address Bit
Name
SR R/W
Function
Comment
10
00FF00
(MPU)
D7
D6
D5
D4
D3
D2
D1
D0
BSMD1
BSMD0
CEMD1
CEMD0
CE3
CE2
CE1
CE0
Bus mode (CPU mode)
Chip enable mode
CE3 (R33)
CE2 (R32)
CE1 (R31)
CE0 (R30)
* Initial setting can
be selected among 3
types (64K, 512K
min and 512K max)
by mask option
setting.
Only for 64K
bus mode
*
1
0
1
R/W
CE3 enable
CE2 enable
CE1 enable
CE0 enable
CE3 disable
CE2 disable
CE1 disable
CE0 disable
BSMD1
1
0
BSMD0
1
0
1
0
Mode
512K (Maximum)
512K (Minimum)
64K
* Option selection
CE signal output
DC (R3x) output
CE signal output Enable/Disable
Enable:
Disable:
00FF01 D7
D6
D5
D4
D3
D2
D1
D0
SPP7
SPP6
SPP5
SPP4
SPP3
SPP2
SPP1
SPP0
Stack pointer page address
< SP page allocatable address >
Single chip mode:
64K mode:
512K (min) mode:
512K (max) mode:
0
R/W
1
0
(MSB)
(LSB)
only 0 page
0–27H page
00FF02
D7
D6
D5
D4
D3
D2
D1
D0
EBR
WT2
WT1
WT0
CLKCHG
OSCC
VDC1
VDC0
Bus release enable register
(K11 and R51 terminal specification)
Wait control register
CPU operating clock switch
OSC3 oscillation On/Off control
Operating mode selection
0
R/W
BREQ
BACK
OSC3
On
WT2
1
0
WT1
1
0
1
0
Number
of state
14
12
10
8
6
4
2
No wait
Input port
Output port
OSC1
Off
K11
R51
VDC1
1
0
VDC0
×
1
0
Operating mode
WT0
1
0
1
0
1
0
1
0
*1
*1 This is just R/W register on S1C88308.
High speed (VD1=3.3V)
Low power (VD1=1.3V)
Normal
(VD1=2.2V)
CEMD1
1
0
CEMD0
1
0
1
0
Mode
64K (CE0)
32K (CE0, CE1)
16K (CE0–CE3)
8K (CE0–CE3)