參數(shù)資料
型號： S1D13706F00A
元件分類： 顯示控制器
英文描述： 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100
封裝： TQFP-100
文件頁數(shù)： 145/171頁
文件大?。?/td> 4940K
代理商： S1D13706F00A
APPENDIX
Appendix 9. Q & A
7751 Group User’s Manual
20–78
Processor mode
If the processor mode is switched as described below by using the processor mode bits (bits 1
and 0 at address 5E16) during program execution, is there any precaution in software?
q Single-chip mode
→ Microprocessor mode
q Memory expansion mode
→ Microprocessor mode
Q
A
If the processor mode is switched as described above by using the processor mode bits, the
mode is switched simultaneously when the cycle to write to the processor mode bits is completed.
Then, the program counter indicates the address next to the address (address XXXX16) that
contains the write instruction for the processor mode bits. Additionally, access to the internal
ROM area is disabled. However, since the instruction queue buffer can prefetch up to three
instructions, the address in the external ROM area and is accessed first after the mode is
switched is one of XXXX16 + 1 to XXXX16 + 4. The instructions at addresses XXXX16 + 1 to
XXXX16 + 3 in the internal ROM area can be executed. To prevent this problem, process the
following by software.
Write the write instruction for the processor mode bits and next instructions (at least three
bytes) at the same addresses both in the internal ROM and external ROM areas. (See
below.)
Transfer the write instruction for the processor mode bits to an internal RAM area and make
a branch to there in order to execute the write instruction. After that, make a branch to the
program address in the external ROM area. (Contents of the instruction queue buffer is
initialized by a branch instruction.)
LDM. B #00000010B, PMR
NOP
LDM. B #00000010B, PMR
NOP
XXXX16
External ROM area
Internal ROM area
XXXX16
At least
three
bytes
:
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