參數(shù)資料
型號(hào)： S25FL004D0LNFI013
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4M X 1 FLASH 3V PROM, DSO8
封裝： 6 X 5 MM, LEAD FREE, MO-229, WSON-8
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 724K
代理商： S25FL004D0LNFI013
16
S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004
Ad va n c e
In f o rm a t i o n
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Pro-
tect (BP2, BP1, BP0) bits are 0.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal
Write Enable Latch. When set to 1, the internal Write Enable Latch is set; when
set to 0, the internal Write Enable Latch is reset and no Write Status Register, Pro-
gram or Erase instruction is accepted.
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy
with a Write Status Register, Program or Erase cycle. This bit is a read only bit
and is read by executing a RDSR instruction. If this bit is 1, such a cycle is in
progress, if it is 0, no such cycle is in progress.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to
the Status Register. Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select
(CS#) Low, followed by the instruction code and the data byte on Serial Data
Input (SI).
The instruction sequence is shown in Figure 8.
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b1 and
b0 of the Status Register. Bits b6, b5 are always read as 0.
Chip Select (CS#) must be driven High after the eighth bit of the data byte has
been latched in. If not, the Write Status Register (WRSR) instruction is not exe-
cuted. As soon as Chip Select (CS#) is driven High, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. At some un-
specified time before the cycle is completed, the Write Enable Latch (WEL) is
reset.
The Write Status Register (WRSR) instruction allows the user to change the val-
ues of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that
is to be treated as read-only, as defined in Table 1. The Write Status Register
(WRSR) instruction also allows the user to set or reset the Status Register Write
Disable (SRWD) bit in accordance with the Write Protect (W#) signal. The Status
Register Write Disable (SRWD) bit and Write Protect (W#) signal allow the device
to be put in the Hardware Protected Mode (HPM). The Write Status Register
(WRSR) instruction cannot be executed once the Hardware Protected Mode (HPM)
is entered.
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