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參數(shù)資料
| 型號： | S29AL008D90MAN010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 512K X 16 FLASH 3V PROM, 90 ns, PDSO44 |
| 封裝： | MO-180AAA, SOP-44 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 2004K |
| 代理商： | S29AL008D90MAN010 |
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February 27, 2009 S29AL008D_00_A11
S29AL008D
29
Data
She e t
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 27).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 9.1 on page 31 shows the outputs for Toggle Bit I on DQ6. Figure 9.2 on page 30 shows the toggle bit
algorithm. Figure 15.9 on page 41 shows the toggle bit timing diagrams. Figure 15.10 on page 42 shows the
differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 29.
9.4
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The
system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 9.1 on page 31 to compare
outputs for DQ2 and DQ6.
Figure 9.2 on page 30 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 29
explains the algorithm. See also DQ6: Toggle Bit I on page 28. Figure 15.9 on page 41 shows the toggle bit
timing diagram. Figure 15.10 on page 42 shows the differences between DQ2 and DQ6 in graphical form.
9.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9.2 on page 30 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 30). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully
completed the program or erase operation. If it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 9.2 on page 30).
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| S29AL008D90MAN011 | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29AL008D90MAN011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MAN012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MAN013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MAN020 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| S29AL008D90MAN021 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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