參數(shù)資料
型號： S29CD032J1JFAI122
廠商： SPANSION LLC
元件分類： PROM
英文描述： 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80
文件頁數(shù)： 74/78頁
文件大小： 1825K
代理商： S29CD032J1JFAI122
74
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
tDH (Data Hold from WE# Rising Edge)
tAS (Address Setup to Falling Edge of WE#)
tAH (Address Hold from Falling Edge of WE#)
tCS (CE# Setup Time)
tCH (CE# Hold Time)
tACS (Address Setup Time to CLK)
tACH (Address Hold Time from ADV# Rising Edge of CLK while ADV# is Low)
Figure: Burst Mode Read (x32 Mode)
Added the following timing parameters
tAAVS
tDVCH
tINDS
tINDH
Figure: Asynchronous Command Write Timing
Changed tOEH to tWEH
Change tWPH to tOEP
Figure: Synchronous Command Write/Read Timing
Removed tWADVH and tWCKS
Figure: WP# Timing
Changed tCH to tBUSY
Table: Erase/Program Operations
Added Note 3: Program/Erase parameters are the same regardless of synchronous or asynchro-
nous mode.
Add tOEP (OE High Pulse)
Alternative CE# Controlled Erase/Program Operations
Removed tOES
Added tWADVS and tWCKS
Appendix 2: Command Definitions
Removed "or when device is in autoselect mode" from Note 14
Rev B0 (June 12, 2006)
Global
Changed document status to Preliminary.
Distinctive Characteristics
Changed cycling endurance from typical to guaranteed.
Performance Characteristics
Updated Max Asynch. Access Time, Max CE# Access Time, and Max OE# Access time in table.
Ordering Information
Updated additional ordering options in designator breakout table. Updated valid combination
tables.
Input/Output Descriptions and Logic Symbols
Changed RY/BY# description.
Physical Dimensions/Connection Diagrams
Changed note on connection diagrams.
相關(guān)PDF資料
PDF描述
S29CD032J1MFAN120 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80
S29CD032J1MQFN133 1M X 32 FLASH 2.7V PROM, 54 ns, PQFP80
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S29CL016J0MFAI113 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL016J0PQFI102 512K X 32 FLASH 3.3V PROM, 54 ns, PQFP80
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