參數(shù)資料
型號: S29GL032M10FFIR23
廠商: SPANSION LLC
元件分類: PROM
英文描述: MirrorBit Flash Family
中文描述: 2M X 16 FLASH 3V PROM, 100 ns, PBGA64
封裝: 13 X 11 MM, LEAD FREE, FORTIFIED, BGA-64
文件頁數(shù): 98/116頁
文件大?。?/td> 6024K
代理商: S29GL032M10FFIR23
80
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
Data
Sheet
AC Characteristics
Read-Only Operations—S29GL256M Only
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 37 for test specifications.
Read-Only Operations—S29GL128M only
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 37 for test specifications.
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std.
10
11
tAVAV
tRC Read Cycle Time (Note 1)
Min
100
ns
tAVQV
tACC Address to Output Delay
CE#, OE# = VIL Max
100
ns
tELQV
tCE Chip Enable to Output Delay
OE# = VIL
Max
100
ns
tPACC Page Access Time
Max
30
ns
tGLQV
tOE Output Enable to Output Delay
Max
30
ns
tEHQZ
tDF Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
tOEH Output Enable Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std.
90
10
tAVAV
tRC Read Cycle Time (Note 1)
Min
90
100
ns
tAVQV
tACC Address to Output Delay
CE#, OE# = VIL Max
90
100
ns
tELQV
tCE Chip Enable to Output Delay
OE# = VIL
Max
90
100
ns
tPACC Page Access Time
Max
25
30
ns
tGLQV
tOE Output Enable to Output Delay
Max
25
30
ns
tEHQZ
tDF Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF Output Enable to Output High Z (Note 1)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
tOEH Output Enable Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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S29GL032M10FFIR30 MirrorBit Flash Family
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