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    參數(shù)資料
    型號(hào): S29PL129N
    廠商: Spansion Inc.
    英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
    中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫(xiě),頁(yè)模式閃存
    文件頁(yè)數(shù): 37/74頁(yè)
    文件大?。?/td> 1968K
    代理商: S29PL129N
    June 6, 2007 S29PL-N_00_A5
    S29PL-N MirrorBit
    Flash Family
    37
    D a t a
    S h e e t
    ( P r e l i m i n a r y )
    7.4.9
    Write Operation Status
    The device provides several bits to determine the status of a program or erase operation. The following
    subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
    DQ7: Data# Polling.
    The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
    is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
    edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last
    word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling
    status on any word other than the last word to be programmed in the write-buffer-page returns false status
    information.
    During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
    programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
    Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
    must provide the program address to read valid status information on DQ7. If a program address falls within a
    protected sector, Data# polling on DQ7 is active for approximately t
    PSP
    , then that bank returns to the read
    mode.
    During the Embedded Erase Algorithm, Data# polling produces a
    0
    on DQ7. When the Embedded Erase
    algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a
    1
    on DQ7.
    The system must provide an address within any of the sectors selected for erasure to read valid status
    information on DQ7.
    After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
    on DQ7 is active for approximately t
    ASP
    , then the bank returns to the read mode. If not all selected sectors are
    protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors
    that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may
    not be valid.
    Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asynchronously
    with DQ6 – DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing
    status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
    the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
    data, the data outputs on DQ6 – DQ0 may be still invalid. Valid data on DQ7 – DQ0 appears on successive
    read cycles.
    See the following for more information:
    Table 7.18,
    Write Operation Status
    on page 40
    , shows the outputs for
    Data# Polling on DQ7.
    Figure 7.4,
    Write Operation Status Flowchart
    on page 38
    , shows the Data# Polling
    algorithm.
    Figure 11.13,
    Data# Polling Timings (During Embedded Algorithms)
    on page 64
    shows the Data#
    Polling timing diagram.
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