參數資料
型號: S374
廠商: Texas Instruments, Inc.
英文描述: OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
中文描述: 八路D型透明鎖存器和邊沿觸發(fā)觸發(fā)器
文件頁數: 7/28頁
文件大?。?/td> 685K
代理商: S374
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B
OCTOBER 1975
REVISED AUGUST 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS
TYP
SN74LS
TYP
UNIT
MIN
MAX
MIN
MAX
VIH
VIL
VIK
High-level input voltage
2
2
V
Low-level input voltage
0.7
0.8
V
Input clamp voltage
VCC = MIN,
VCC = MIN,
VIL = VIL max,
II =
18 mA
VIH = 2 V,
IOH = MAX
1.5
1.5
V
VOH
High level output voltage
High-level output voltage
2 4
2.4
3 4
3.4
2 4
2.4
3 1
3.1
V
VOL
Low level output voltage
Low-level output voltage
VCC = MIN,
VIL = VIL max
VIH = 2 V,
IOL = 12 mA
IOL = 24 mA
0.25
0.4
0.25
0.4
V
0.35
0.5
IOZH
Off-state output current,
high-level voltage applied
VCC = MAX,
VO = 2.7 V
VCC = MAX,
VO = 0.4 V
VIH = 2 V,
20
20
A
IOZL
Off-state output current,
low-level voltage applied
VIH = 2 V,
A
20
20
II
Input current at maximum
input voltage
VCC= MAX
VCC = MAX,
VI= 7 V
VI = 7 V
0 1
0.1
0 1
0.1
mA
IIH
IIL
IOS
High-level input current
VCC = MAX,
VCC = MAX,
VCC = MAX
VCC = MAX,
Output control at 4.5 V
VI = 2.7 V
VI = 0.4 V
20
20
A
Low-level input current
Short-circuit output current
§
0.4
0.4
mA
30
130
30
130
mA
ICC
Supply current
LS373
24
40
24
40
mA
LS374
27
40
27
40
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
°
C.
§
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, V
CC
= 5 V, T
A
= 25
°
C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
TEST CONDITIONS
LS373
TYP
LS374
TYP
UNIT
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
RL = 667
CL = 45 pF,
See Note 3
35
50
MHz
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Data
Any Q
RL = 667
CL
See Note 3
12
18
ns
,
12
18
C or CLK
Any Q
RL = 667
CL
See Note 3
20
30
15
28
ns
,
18
30
19
28
OC
Any Q
RL = 667
CL
See Note 3
15
28
20
26
ns
,
25
36
21
28
15
25
15
28
OC
Any Q
RL = 667
CL = 5 pF
ns
12
20
12
20
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
fmax= maximum clock frequency
tPLH= propagation delay time, low-to-high-level output
tPHL= propagation delay time, high-to-low-level output
tPZH= output enable time to high level
tPZL= output enable time to low level
tPHZ= output disable time from high level
tPLZ= output disable time from low level
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