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參數(shù)資料
| 型號(hào)： | S3C3410XXX-QA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, QFP-128 |
| 文件頁(yè)數(shù)： | 57/314頁(yè) |
| 文件大小： | 1701K |
| 代理商： | S3C3410XXX-QA |
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S3C3410X RISC MICROPROCESSOR
PRODUCT OVERVIEW
1-11
PIN DESCRIPTIONS
Table 1-3. S3C3410X Pin Descriptions
Pin
I/O
Description
BUS CONTROLLER
TEST[1:0]
I
The TEST[1:0] can configure the data bus size for bank 0 in normal or MDS mode.
The normal mode is for CPU to start its operation by fetching the instruction from
external memory. The MDS mode is for CPU to be debugged by the external
Emulator, EmbeddedICE, etc.
00 = Normal mode with 8-bit data bus size for bank 0 access.
01 = Normal mode with 16-bit data bus size for bank 0 access.
10 = MDS mode with 8-bit data bus size for bank 0 access.
11 = MDS mode with 16-bit data bus size for bank 0 access.
A[23:0]
O
A[23:0] (address bus) generate the address when external memory access.
D[15:0]
I/O
D[15:0] (Data bus) input the data during memory read and output the data during
memory write. The data bus width can be programmable for 8-bit or 16-bit by the
BANKCONx register option.
nCS[7:0]
O
nCS[7:0] (Chip Select) selectively generate the chip select signal of each bank when
the external memory access address is within the address range of each bank. The
number of access cycle and the bank size can be programmable by the BANKCONx
register option.
nECS[1:0]
O
nECS[1:0] (External Chip Select) generate the external chip select signal for the
extra device (External I/O device).
nOE
O
nOE (Output Enable) indicates that the current bus cycle is a read cycle.
nWE
O
nWE (Write Enable for x16 SRAM or SDRAM) indicates that the current bus cycle is
a write cycle. To support the byte write to external memory, the byte to be accessed
can be determined by nBE[1:0], which is the selection on upper byte or lower byte.
For example, in case of 16-bit SRAM, nBE[1:0] should play it role as UB(Upper
Byte)/LB(Lower Byte) to select the upper byte or lower byte. In case of SDRAM,
nWBE[1:0] should play it role as DQM[1:0] to select the upper byte or lower byte. For
16-bit access, not 8-bit access, both nWBE[1:0] should be activated at same time. In
certain case, no more byte access is needed. For example, x16 Flash Memory does
not need byte access through 16-bit bus when user need the programming in the
flash memory. In this case, please use nWBE[0] instead of nWE to indicate that the
current bus cycle is a write cycle. Summarizing, nWE should be used to indicate the
write bus cycle in case of x16 SRAM and x16/x8 SDRAM. In case of x16 with two x8
SRAM, nWBE[0] and nWBE[1] should be connected to the WE of SRAM,
respectively. For more detail information, please refer the chapter 4.
nWBE[1:0]
O
nWBE[1:0] (Write Byte Enable). In case of Flash or ROM access, nWBE[0] should
be connected to the WE of memory. For the access to the non-volatile memory, we
do not need the selection on bytes because the 8-bit write cycle via 16-bit bus is no
more necessary. To program the data into the non-volatile memory, we should
always use the 16-bit access. In this configuration, please use nWBE[0] instead of
nWE to indicate that the current bus cycle is a write cycle. Summarizing, nWBE[0]
should be used to indicate the current write bus cycle in case of x8 SRAM, x8/x16
ROM, EDODRAM or Flash memory. For more detail information, please refer the
chapter 4.
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相關(guān)代理商/技術(shù)參數(shù) |
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| S3-C3-5V | 制造商:Panasonic Electric Works 功能描述: |
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