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參數(shù)資料
| 型號(hào)： | S42WD61SBP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dual Voltage Supervisory Circuit With Watchdog Timer |
| 中文描述： | 雙電壓監(jiān)控電路，帶有看門(mén)狗定時(shí)器 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | S42WD61SBP |
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2
S4242/S42WD42/S4261/S42WD61
2025 6.0 4/17/00
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias
Storage Temperature
Soldering Temperature (less than 10 seconds) ...................................................................................................................300
°
C
Supply Voltage
............................................................................................................................................................. 0 to 6.5V
Voltage on Any Pin
....................................................................................................................................... -0.3V to V
CC
+0.3V
ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
............................................................................................................................... -40
°
C to +85
°
C
..................................................................................................................................... -65
°
C to +125
°
C
2.7V to 4.5V
4.5V to 5.5V
Symbol
Parameter
Conditions
Min
Max
Min
Max
Units
f
SCL
SCL Clock Frequency
0
100
400
KHz
t
LOW
Clock Low Period
4.7
1.3
μs
t
HIGH
Clock High Period
4.0
0.6
μs
t
BUF
Bus Free Time
Before New Transmission
4.7
1.3
μs
t
SU:STA
Start Condition Setup Time
4.7
0.6
μs
t
HD:STA
Start Condition Hold Time
4.0
0.6
μs
t
SU:STO
Stop Condition Setup Time
4.7
0.6
μs
t
AA
Clock to Output
SCL Low to SDA Data Out Valid
0.3
3.5
0.2
0.9
μs
t
DH
Data Out Hold Time
SCL Low to SDA Data Out Change
0.3
0.2
μs
t
R
SCL and SDA Rise Time
1000
300
ns
t
F
SCL and SDA Fall Time
300
300
ns
t
SU:DAT
Data In Setup Time
250
100
ns
t
HD:DAT
Data In Hold Time
0
0
ns
T
I
Noise Spike Width
@ SCL, SDA Inputs
Noise Suppression Time Constant
100
100
ns
t
WR
Write Cycle Time
10
10
ms
AC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
2025 PGM T3.0
2025 PGM T2.0
DC ELECTRICAL CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
SCL = CMOS Levels @ 100KHz
SDA = Open
All other inputs = GND or V
CC
V
CC
=5.5V
3
mA
I
CC
Supply Current (CMOS)
V
CC
=3.3V
V
CC
=5.5V
V
CC
=3.3V
2
mA
μA
μA
I
SB
Standby Current (CMOS)
SCL = SDA = V
All other inputs = GND
50
25
I
LI
Input Leakage
V
IN
= 0 To V
CC
10
μA
I
LO
Output Leakage
V
OUT
= 0 To V
CC
10
μA
V
IL
Input Low Voltage
SCL, SDA, RESET# (pin 2)
0.3xV
CC
V
V
IH
Input High Voltage
SCL, SDA, RESET (pin7)
0.7xV
CC
V
V
OL
Output Low Voltage
I
OL
= 3mA SDA
0.4
V
Temperature
Commercial
Industrial
Min
0
°
C
-40
°
C
Max
+70
°
C
+85
°
C
RECOMMENDED OPERATING CONDITIONS
2025 PGM T1.0
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相關(guān)代理商/技術(shù)參數(shù) |
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| S42WD61SBS | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Dual Voltage Supervisory Circuit With Watchdog Timer |
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| S42WD61SS | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Dual Voltage Supervisory Circuit With Watchdog Timer |
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