![](http://datasheet.mmic.net.cn/260000/S5K437CA_datasheet_15972202/S5K437CA_23.png)
1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
19
OPERATION DESCRIPTION
1. Output Data Format
1-1. Main Clock Divider
All the data output and sync signals are synchronized to data clock output (
DCLK
). It is generated as the main
clock input (
MCLK
) is divided. The dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register
(
mcdiv
). For 10-bit ADC and VGA resolution, dividing ratio of more than 2 is required. If ratio of 1 is used, the duty
must be within 40% to 60%.
1-2. Synchronous Signal Output
The horizontal sync (
HSYNC
) and vertical sync (
VSYNC
) signals are also available. The sync pulse width, polarity
and position are programmable on the control registers (ref. timing chart). When display mode is activated, the
sync signal outputs indicate that the output data is valid (
hsdisp
= 1) or the output rows are valid (
vsdisp
= 1).
1-3. Window of Interest Control
Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned
anywhere on the pixel array. It is composed of four values: row start pointer (
wrp
), column start pointer (
wcp
),
row depth(
wrd
) and column width (
wcw
). Each value can be programmed on the control registers. For
convenience of color signal processing,
wcp
is truncated to even numbers so that the starting data of each line is
on the red and green column of Bayer pattern. Figure 4 illustrates the WOI on the displayed pixel image.
Window Of Interest
(wcp,wrp)
wcw
w
0
687
507
Figure 4. WOI definition
1-4. Vertical Mirror and Horizontal Mirror Mode Control
The pixel data are normally read out from left to right in horizontal direction and from top to bottom in vertical
direction. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be
flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to
top in vertical mirror mode. The horizontal and the vertical mirror mode can be programmed on the Horizontal
Mirror Control Register (
mirch
) and Vertical Mirror Control Register (
mircv
).
1-5. Sub-sampling Control
The pixel data in sub-sampling rate can be read out in both horizontal and vertical direction. Sub-sampling can be
done in four rates : full, 1/2, 1/3 and 1/4. You can control the sub-sampling on the Sub-sampling Control
Registers,
subsr
and
subsc
. The sub-sampling is performed only in the Bayer space.