參數(shù)資料
型號： S5L9284D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 6/24頁
文件大?。?/td> 350K
代理商： S5L9284D
S5L9284D
DIGITAL SIGNAL PROCESSOR
6
NOTES
:
1.
2.
3.
PBFR: 7.35 kHz Write frame clock produced by data which is being reproduced.
/PBCK : Channel bit clock of data which being reproduced.
/JIT : Display signal of either RAM overflow or underflow for
±
4 frame jitter margin.
63
SEL3
I
CD-ROM selection terminal (
“
L
”
: CDP,
“
H
”
: CD-ROM)
64
SEL4
I
SRAM selection terminal (
“
L
”
: internal SRAM,
“
H
”
: external SRAM)
65
TEST1
I
Test terminal (
“
L
”
: normal,
“
H
”
: test)
66
EFMI
I
EFM data input
67
APDO1
O
Charge pump output for analog PLL
68
/ISTAT
O
The internal status output
69
TRCNT
I
Tracking clock input signal
70
LOCK
O
Output signal of LKFS conditions sampled PBFR/16
(If LKFS is High, lock is High. If the LKFS is sampled Low at least 8 times by
PBFR/16, lock is Low )
71
PBFR
O
Write frame clock (Lock : 7.35kHz)
72
SMEF
O
LPF time constant control of the spindle servo error signal
73
SMON
O
ON/OFF control signal for spindle servo
74
DV
DD2
Digital supply voltage 2
75
SMDP
O
Spindle motor driving output (rough control in the speed mode, phase control in
the phase mode
76
SMSD
O
Spindle motor (Velocity control in the phase mode)
77
VCOO
O
VCO output
78
VCOI
I
VCO inut (when in locked status by means of PBFR, it is 8.6436MHz)
79
DSPEED
I
Double speed mode control (
“
H
”
: normal speed,
“
L
”
: 2-times speed )
80
APDO2
O
Analog PLL charge pump output for double speed mode
PIN DESCRIPTION
(Continued)
Pin No.
Symbol
I/O
Description
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